PDF LT1640HIS8 Data sheet ( Hoja de datos )

Número de pieza	LT1640HIS8
Descripción	Negative Voltage Hot Swap Controller
Fabricantes	Linear Technology
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No Preview Available ! FEATURES s Allows Safe Board Insertion and Removal from a Live – 48V Backplane s Operates from –10V to – 80V s Programmable Inrush Current s Programmable Electronic Circuit Breaker s Programmable Overvoltage Protection s Programmable Undervoltage Lockout s Power Good Control Output U APPLICATIONS s Central Office Switching s – 48V Distributed Power Systems s Negative Power Supply Control LT1640L/LT1640H Negative Voltage Hot Swap Controller DESCRIPTION The LT®1640L/LT1640H is an 8-pin, negative voltage Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable electronic circuit breaker protects the system against shorts. The PWRGD (LTC1640L) or PWRGD (LTC1640H) signal can be used to directly enable a power module. The LT1640L is designed for modules with a low enable input and the LT1640H for modules with a high enable input. The LT1640L/LT1640H is available in 8-pin PDIP and SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. TYPICAL APPLICATION GND UV = 37V OV = 71V R4 562k 1% R5 9.09k 1% R6 10k 1% 3 UV 2 OV VEE 4 SENSE 5 – 48V R1 0.02Ω 5% 8 VDD LT1640L 1 PWRGD GATE DRAIN C1 33nF 24V 6 R2 10Ω 5% R3 10k C2 5% 3.3nF 100V 7 Q1 IRF530 C3 + 0.1µF 100V C4 100µF 100V 2 1 ON/OFF VIN+ VOUT+ SENSE + 9 8 TRIM 7 SENSE – 6 4 VIN– VOUT– 5 + 5V C5 100µF 16V LUCENT JW050A1-E 1640 TA01 Input Inrush Current CONTACT BOUNCE 1640 F07b 1 1 page LT1640L/LT1640H PIN FUNCTIONS UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.223V high to low threshold, an under- voltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.243 low to high threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the circuit breaker will trip when the voltage across the resistor exceeds 50mV. Noise spikes of less than 2µs are filtered out and will not trip the circuit breaker. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, VEE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low and (VSENSE – VEE) < 50mV. The GATE pin is pulled high by a 45µA current source and pulled low with a 50mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel and the V – pin of the power module. When the DRAIN pin is below VPG, the PWRGD or PWRGD pin will toggle. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. The input supply voltage ranges from 10V to 80V. BLOCK DIAGRA – UV + REF – + OV 50mV –+ – + VEE SENSE VDD VCC AND REFERENCE GENERATOR VCC REF OUTPUT DRIVE PWRGD/PWRGD LOGIC AND GATE DRIVE GATE +– +– VPG VEE DRAIN 1640 BD 5 5 Page LT1640L/LT1640H APPLICATIONS INFORMATION GND LT1640H R4 3 UV + R5 +– VPG 2 OV – R6 VEE SENSE 45 8 VDD PWRGD 1 R7 5k Q2 + Q3 VEE DRAIN 7 GATE 6 R3 C1 R2 C2 ACTIVE LOW ENABLE MODULE VIN+ VOUT+ ON/OFF C3 VIN– VOUT– R1 – 48V Q1 1640 F11 Figure 11. Active High Enable Module GND LT1640L R4 3 UV + R5 2 +– VPG – OV R6 VEE SENSE 45 8 VDD PWRGD 1 + Q2 VEE DRAIN 7 GATE 6 R3 C1 R2 C2 ACTIVE LOW ENABLE MODULE VIN+ VOUT+ ON/OFF C3 VIN– VOUT– – 48V R1 Q1 1640 F12 Figure 12. Active Low Enable Module pull-up current in the module then flows through R7, pulling the PWRGD pin high and enabling the module. When the DRAIN voltage of the LT1640L is high with respect to VEE, the internal pull-down transistor Q2 is off and the PWRGD pin is in a high impedance state (Figure 12). The PWRGD pin will be pulled high by the module’s internal pull-up current source, turning the module off. When the DRAIN voltage drops below VPG, Q2 will turn on and the PWRGD pin will pull low, enabling the module. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good as shown in Figure 13. Gate Pin Voltage Regulation When the supply voltage to the chip is more than 15.5V, the GATE pin voltage is regulated at 13.5V above VEE. If the supply voltage is less than 15.5V, the GATE voltage will be about 2V below the supply voltage. At the minimum 10V supply voltage, the gate voltage is guaranteed to be greater than 6V. The gate voltage will be no greater than 18V for supply voltages up to 80V. GND R4 562k 1% R5 9.09k 1% R6 10k 1% – 48V 3 UV 2 OV VEE 4 SENSE 5 R1 0.02Ω 5% 8 VDD LT1640L 1 PWRGD GATE DRAIN C1 0.033µF 24V 67 R2 R3 10Ω 10k C2 5% 5% 3.3nF 100V Q1 IRF530 R7 51k 5% 4N25 Figure 13. Using PWRGD to Drive an Optoisolator PWRGD + C3 100µF 100V 1640 F13 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 11 Page

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