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부품번호 | DPS128M8 기능 |
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기능 | 128kx8 High Speed CMOS SRAM | ||
제조업체 | Dense-Pac Microsystems | ||
로고 | |||
전체 10 페이지수
1 Megabit High Speed CMOS SRAM
DPS128M8CnY/BnY, DPS128X8CA3/BA3
DESCRIPTION:
The DPS128M8CnY/BnY, DPS128X8CA3/BA3 High Speed SRAM
devices are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages,
or mounted on a 50-pin PGA co-fired ceramic substrate. These devices
pack 1-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in2, while maintaining a total height as low as 0.082 inches.
The SLCC devices contain an individual 128K x 8 SRAMs, each
packaged in a hermetically sealed SLCC, making the modules suitable
for commercial, industrial and military applications.
The DPS128M8BnY/DPS128X8BA3 has one active low Chip Enable
(CE) while the DPS128M8CnY/DPS128X8CA3 has an active low Chip
Enable (CE) and an active high Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC
‘’I’’ Leaded
SLCC
FEATURES:
• Organization Available: 128Kx8
• Access Times: 20*, 25, 30, 35, 45ns
• Fully Static Operation - No clock or refresh required
• Single +5V Power Supply, ±10% Tolerance
• TTL Compatible
• Common Data Inputs and Outputs
• Low Data Retention Voltage: 2.0V min.
• Packages Available:
‘’J’’ Leaded
SLCC
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin ‘’J’’ Leaded SLCC
48 - Pin Gullwing Leaded SLCC
50 - Pin PGA Dense-Stack
w * Commercial only.
ww. Dense-Stack
Gullwing
Leaded SLCC
DataSheet430A097-31
U.comREV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS128M8CnY/BnY, DPS128X8CA3/BA3
Dense-Pac Microsystems, Inc.
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
0V to 3.0V
5ns
1.5V
Load
1
2
CL
100pF
5pF
OUTPUT LOAD
Parameters Measured
except tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ
tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ
NOTE: tLZ2 and tHZ2 apply to DPS128M8CnY/DPS128X8CA3 version only.
Figure 1. Output Load
* Including Probe and Jig Capacitance.
+5V
DOUT
CL*
480Ω
255Ω
Symbol
VDR
VCDR
tR
Parameter
VDD for Data
Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Data Retention AC Characteristics 8
Test Conditions
CE ≥ VDR -0.2V, (SEL ≥ VDR -0.2V,
or VIN ≤ VDR -0.2V or VIN ≤ 0.2V)
See Data Retention Waveform
See Data Retention Waveform
NOTE: Test Conditions in parenthesis apply to DPS128M8CnY/DPS128X8CA3 version only.
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
2.3V
VDR1
CE
0V
CE ≥ VDD -0.2V
DATA RETENTION WAVEFORM: SEL Controlled. (Applies to DPS128M8CnY/DPS128X8CA3 only)
VDD
4.5V
SEL
VDR2
0.4V
0V
SEL ≤ -0.2V
4 30A097-31
REV. D
4페이지 Dense-Pac Microsystems, Inc.
DPS128M8CnY/BnY, DPS128X8CA3/BA3
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 2: WE Controlled. OE is HIGH. 8, 9
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3: WE Controlled. OE is LOW. 8, 9
30A097-31
REV. D
7
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
DPS128M8 | 128kx8 High Speed CMOS SRAM | Dense-Pac Microsystems |
DPS128M8xxx | 128kx8 High Speed CMOS SRAM | Dense-Pac Microsystems |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |