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DPS128M8xxx 데이터시트 PDF




Dense-Pac Microsystems에서 제조한 전자 부품 DPS128M8xxx은 전자 산업 및 응용 분야에서
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부품번호 DPS128M8xxx 기능
기능 128kx8 High Speed CMOS SRAM
제조업체 Dense-Pac Microsystems
로고 Dense-Pac Microsystems 로고


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DPS128M8xxx 데이터시트, 핀배열, 회로
1 Megabit High Speed CMOS SRAM
DPS128M8CnY/BnY, DPS128X8CA3/BA3
DESCRIPTION:
The DPS128M8CnY/BnY, DPS128X8CA3/BA3 High Speed SRAM
devices are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages,
or mounted on a 50-pin PGA co-fired ceramic substrate. These devices
pack 1-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in2, while maintaining a total height as low as 0.082 inches.
The SLCC devices contain an individual 128K x 8 SRAMs, each
packaged in a hermetically sealed SLCC, making the modules suitable
for commercial, industrial and military applications.
The DPS128M8BnY/DPS128X8BA3 has one active low Chip Enable
(CE) while the DPS128M8CnY/DPS128X8CA3 has an active low Chip
Enable (CE) and an active high Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC
‘’I’’ Leaded
SLCC
FEATURES:
Organization Available: 128Kx8
Access Times: 20*, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply, ±10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage: 2.0V min.
Packages Available:
‘’J’’ Leaded
SLCC
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin ‘’J’’ Leaded SLCC
48 - Pin Gullwing Leaded SLCC
50 - Pin PGA Dense-Stack
w * Commercial only.
ww. Dense-Stack
Gullwing
Leaded SLCC
DataSheet430A097-31
U.comREV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1




DPS128M8xxx pdf, 반도체, 판매, 대치품
DPS128M8CnY/BnY, DPS128X8CA3/BA3
Dense-Pac Microsystems, Inc.
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
0V to 3.0V
5ns
1.5V
Load
1
2
CL
100pF
5pF
OUTPUT LOAD
Parameters Measured
except tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ
tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ
NOTE: tLZ2 and tHZ2 apply to DPS128M8CnY/DPS128X8CA3 version only.
Figure 1. Output Load
* Including Probe and Jig Capacitance.
+5V
DOUT
CL*
480
255
Symbol
VDR
VCDR
tR
Parameter
VDD for Data
Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Data Retention AC Characteristics 8
Test Conditions
CE VDR -0.2V, (SEL VDR -0.2V,
or VIN VDR -0.2V or VIN 0.2V)
See Data Retention Waveform
See Data Retention Waveform
NOTE: Test Conditions in parenthesis apply to DPS128M8CnY/DPS128X8CA3 version only.
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
2.3V
VDR1
CE
0V
CE VDD -0.2V
DATA RETENTION WAVEFORM: SEL Controlled. (Applies to DPS128M8CnY/DPS128X8CA3 only)
VDD
4.5V
SEL
VDR2
0.4V
0V
SEL -0.2V
4 30A097-31
REV. D

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DPS128M8xxx 전자부품, 판매, 대치품
Dense-Pac Microsystems, Inc.
DPS128M8CnY/BnY, DPS128X8CA3/BA3
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 2: WE Controlled. OE is HIGH. 8, 9
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3: WE Controlled. OE is LOW. 8, 9
30A097-31
REV. D
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관련 데이터시트

부품번호상세설명 및 기능제조사
DPS128M8xxx

128kx8 High Speed CMOS SRAM

Dense-Pac Microsystems
Dense-Pac Microsystems

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