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PDF M30302MCP-xxx Data sheet ( Hoja de datos )
| Número de pieza | M30302MCP-xxx | |
| Descripción | (M30302Mx) Single-Chip 16-Bit CMOS Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
REJ03B0088-0080
Rev.0.80
Mar 18, 2005
1. Overview
The M16C/30P Group of single-chip microcomputers are built using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this
microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it
suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/
logic operations.
1.1 Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.0.80 Mar 18, 2005 Page 1 of 34
REJ03B0088-0080
1 page  
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/30P Group
1.5 Pin Configuration
Figures 1.3 to 1.4 show the pin configurations (top view).
PIN CONFIGURATION (top view)
1. Overview
P0_7/AN0_7
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 49
83 48
84 47
85 46
86 45
87 44
88 43
89 42
90 41
91
M16C/30P Group
40
92 39
93 38
94 37
95 36
96 35
97 34
98 33
99 32
100 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/30P on VCC1=VCC2.
Figure 1.3 Pin Configuration (Top View)
Package : 100P6S-A
Rev.0.80 Mar 18, 2005 Page 5 of 34
REJ03B0088-0080
5 Page 
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/30P Group
2. Central Processing Unit (CPU)
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
Rev.0.80 Mar 18, 2005 Page 11 of 34
REJ03B0088-0080
11 Page | ||
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