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ST93C06C 데이터시트 PDF




ST Microelectronics에서 제조한 전자 부품 ST93C06C은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ST93C06C 자료 제공

부품번호 ST93C06C 기능
기능 256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM
제조업체 ST Microelectronics
로고 ST Microelectronics 로고


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ST93C06C 데이터시트, 핀배열, 회로
ST93C06
ST93C06C
256 bit (16 x 16 or 32 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
DUAL ORGANIZATION: 16 x 16 or 32 x 8
BYTE/WORD and ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE 5V ±10% SUPPLY VOLTAGE
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
PERFORMANCES for ”C” VERSION
ST93C06 and ST93C06C are replaced by
the M93C06
8
1
PSDIP8 (B)
0.4mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST93C06 and ST93C06C are 256 bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. In the text the
two products are referred to as ST93C06.
The memory is divided into either 32 x 8 bit bytes
or 16 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
The memory is accessed through a serial input (D)
and by a set of instructions which includes Read a
byte/word, Write a byte/word, Erase a byte/word,
Erase All and Write All. ARead instruction loads the
address of the first byte/word to be read into an
internal address pointer.
Table 1. Signal Names
S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG
Organisation Select
VCC Supply Voltage
VSS Ground
D
C
S
ORG
VCC
ST93C06
ST93C06C
VSS
Q
AI00816B
June 1997
This is information on a product still in production bu t not recommended for new de signs.
1/15




ST93C06C pdf, 반도체, 판매, 대치품
ST93C06, ST93C06C
Table 5. AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 5V ± 10%)
Symbol Alt
Parameter
Test Condition
Min Max Unit
tSHCH
tCSS Chip Select High to Clock High
50 ns
tCLSH
tDVCH
tSKS Clock Low to Chip Select High
tDIS Input Valid to Clock High
100 ns
100 ns
tCHDX
tDIH Clock High to Input Transition
Temp. Range: grade 1
Temp. Range:
grades 3, 6
100
200
ns
ns
tCHQL
tCHQV
tPD0 Clock High to Output Low
tPD1 Clock High to Output Valid
500 ns
500 ns
tCLSL
tCSH Clock Low to Chip Select Low
0 ns
tSLCH
tSLSH
Chip Select Low to Clock High
tCS Chip Select Low to Chip Select High
Note 1
250
250
ns
ns
tSHQV
tSLQZ
tSV Chip Select High to Output Valid
tDF Chip Select Low to Output Hi-Z
ST93C06
ST93C06C
500 ns
300 ns
200 ns
tCHCL
tSKH Clock High to Clock Low
Note 2
250
ns
tCLCH
tSKL Clock Low to Clock High
Note 2
250
ns
tW tWP Erase/Write Cycle time
10 ms
fC fSK Clock Frequency
0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
tCLSH
C
tCLCH
tSHCH
S
tDVCH
D
tCHCL
START
tCHDX
OP CODE OP CODE OP CODE OP CODE
START
OP CODE INPUT
AI00819C
4/15

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ST93C06C 전자부품, 판매, 대치품
ST93C06, ST93C06C
Figure 6. READ, WRITE, EWEN, EWDS Sequences
READ
S
D 1 1 0 X X An A0
Q Qn
Q0
OP
CODE ADDR
DATA OUT
WRITE
S
D
Q
1 0 1 X X An A0 Dn
CHECK
STATUS
D0
OP
CODE ADDR
DATA IN
BUSY
READY
ERASE
WRITE
ENABLE
S
D
1 0 0 1 1 Xn X0
ERASE S
WRITE
DISABLE
D
1 0 0 0 0 Xn X0
OP
CODE
OP
CODE
AI00822D
Notes: 1. An: n = 3 for x16 org. and 4 for x8 org.
2. Xn: n = 3 for x16 org. and 4 for x8 org.
If the ST93C06 is still performing the erase cycle,
the Busy signal (Q = 0) will be returned if S is driven
high, and the ST93C06 will ignore any data on the
bus. When the erase cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93C06 is ready to receive a new instruction.
Write
The Write instruction (WRITE) is followed by the
address and the 8 or 16 data bits to be written. Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C) in order to start the
self-timed programming cycle. If the ST93C06 is
still performing the write cycle, the Busy signal (Q
= 0) will be returned if S is driven high, and the
ST93C06 will ignore any data on the bus. When the
write cycle is completed, the Ready signal (Q = 1)
will indicate (if S is driven high) that the ST93C06
is ready to receive a new instruction. Programming
is internally self-timed (the external clock signal on
C input may be disconnected or left running after
the start of a programming cycle) and does not
require an Erase instruction prior to the Write in-
struction (The Write instruction includes an auto-
matic erase cycle before programing data).
7/15

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관련 데이터시트

부품번호상세설명 및 기능제조사
ST93C06

256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM

ST Microelectronics
ST Microelectronics
ST93C06C

256 bit 16 x 16 or 32 x 8 SERIAL MICROWIRE EEPROM

ST Microelectronics
ST Microelectronics

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