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PDF AD9446 Data sheet ( Hoja de datos )
| Número de pieza | AD9446 | |
| Descripción | 16-Bit 80/100 MSPS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9446 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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Preliminary Technical Data
16-Bit, 80/100 MSPS, A/D Converter
AD9446
FEATURES
100 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 30 MHz and 31 MHz
81.6 dB SNR with 30 MHz input (3.2 V p-p input, 80Msps)
90 dBc SFDR with30 MHz input (3.2 V p-p input, 80Msps)
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±3.0 LSB typical
2.3 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p to 3.2 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos compliment)
Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9446 is a 16-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for power, small size, and ease of use. The product
w operates at up to a 100 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
w cellular infrastructure equipment.
wThe ADC requires 3.3 V and 5.0 V power supplies and a low
.Dvoltage differential input clock for full performance operation.
No external reference or driver components are required for
amany applications. Data outputs are LVDS-compatible (ANSI-
t644) or CMOS-compatible and include the means to reduce
athe overall current needed for short trace distances.
Sheet4Rev. PrF
UInformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
.infringements of patents or other rights of third parties that may result from its use.
cSpecifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
omregistered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
VIN+
VIN-
CLK+
CLK-
AGND AVDD1 AVDD2 DRGND DRVDD
AD9446
BUFFER
T/H
CLOCK
&TIMING
MANAGEMENT
PIPELINE
ADC
REF
CMOS
16 OR LVDS
OUTPUT
STAGING
2
32
2
DFS
DCS MODE
OUTPUT
MODE
OR
D15-
D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9446 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. True 16 bit linearity.
2. High performance: outstanding SFDR performance for multi-
carrier, multimode 3G and 4G cellular base station receivers.
3. Ease of use: on-chip reference and track-and-hold. An
output clock simplifies data capture.
4. Packaged in a Pb-free, 100-lead TQFP/EP.
5. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
6. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
Parameter
WORST SPUR EXCLUDING SECOND
OR THIRD HARMONICS
fIN = 10 MHz
fIN = 10 MHz (2 V p-p)
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR
fIN = 10.8 MHz @ −7 dBFS,
9.8 MHz @ −7 dBFS
fIN = 70.3 MHz @ −7 dBFS,
69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
AD9446
Test AD9446BSVZ-80
Temp Level Min Typ Max
AD9446BSVZ-100
Min Typ Max
Unit
25°C IV
Full IV
25°C IV
Full IV
25°C I
Full IV
25°C IV
Full IV
25°C V
25°C V
25°C V
Full V
−95
−95
−90
−90
−85
95
325
−96 dBc
dBc
−95 dBc
dBc
−95 dBc
dBc
−95 dBc
dBc
−94 dBc
95 dBFS
dBFS
540 MHz
Rev. PrF | Page 5 of 24
5 Page 
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DCS MODE 1
DNC 2
OUTPUT MODE 3
DFS 4
LVDS_BIAS 5
AVDD1 6
SENSE 7
VREF 8
AGND 9
REFT 10
REFB 11
AVDD2 12
AVDD2 13
AVDD2 14
AVDD2 15
AVDD2 16
AVDD2 17
AVDD1 18
AVDD1 19
AVDD1 20
AGND 21
VIN+ 22
VIN- 23
AGND 24
AVDD2 25
AD9446 Pinout
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
AD9446
75 DRGND
74 D10+
73 D10-
72 D9+
71 D9-
70 D8+
69 D8-
68 DCO+
67 DCO-
66 D7+
65 D7-
64 DRVDD
63 DRGND
62 D6+
61 D6-
60 D5+
59 D5-
58 D4+
57 D4-
56 D3+
55 D3-
54 D2+
53 D2-
52 D1+
51 D1-
Rev. PrF | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9446.PDF ] | |
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