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AD9444 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9444은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AD9444 기능
기능 14-Bit 80 MSPS A/D Converter
제조업체 Analog Devices
로고 Analog Devices 로고


AD9444 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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AD9444 데이터시트, 핀배열, 회로
FEATURES
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical
1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
w for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
wwThe ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
.DNo external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
a644) or CMOS-compatible and include the means to reduce
tthe overall current needed for short trace distances.
aSheet4Rev. 0
UInformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
.infringements of patents or other rights of third parties that may result from its use.
cSpecifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
omregistered trademarks are the property of their respective owners.
14-Bit, 80 MSPS, A/D Converter
AD9444
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
AD9444
VIN+
VIN–
BUFFER
T/H
CLK+
CLK–
CLOCK
AND TIMING
MANAGEMENT
14
PIPELINE
ADC
CMOS
OR
LVDS
OUTPUT
STAGING
2
28
2
REF
DFS
DCS MODE
OUTPUT MODE
OR
D13–D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD9444 pdf, 반도체, 판매, 대치품
AD9444
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
WORST SPUR EXCLUDING SECOND OR HARMONICS
fIN = 10 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR
fIN = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS
fIN = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
Temp
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
Test Level
IV
IV
I
IV
IV
IV
V
IV
IV
I
IV
IV
IV
V
V
V
V
V
IV
IV
I
IV
IV
IV
V
IV
IV
I
IV
IV
IV
V
IV
IV
I
IV
IV
IV
V
V
V
V
AD9444BSVZ-80
Min Typ
Max
73.0 74.0
72.7
72.4 73.7
72.3
72.3 73.1
72.0
72.3
73.0 74.0
72.7
72.4 73.7
72.2
72.2 73.1
72.0
72.3
12.1
12.0
11.9
11.8
91 97
87
91 97
87
90 97
87
96
−97 −91
−87
−97 −91
−87
−97 −90
−87
−96
−102
−103
−102
−99
−93
−93
−93
−93
−93
−93
−102
−100
650
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
MHz
Rev. 0 | Page 4 of 40

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AD9444 전자부품, 판매, 대치품
VIN
CLK–
CLK+
DX
DCO+
DCO–
N
N–1
tCLKL
tCLKH
tPD
N+1
N+2
12 CYCLES
N-12
N-11
N-1 N
tDCOPD
Figure 3. CMOS Timing Diagram
AD9444
EXPLANATION OF TEST LEVELS
Test Level
I
II
III
IV
V
VI
Definitions
100% production tested.
100% production tested at 25°C and sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 7 of 40

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