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NHPXA270 데이터시트, 핀배열, 회로
Intel® PXA270 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
High-performance processor:
— Intel XScale® microarchitecture with
Intel® Wireless MMX™ Technology
— 7 Stage pipeline
— 32 KB instruction cache
— 32 KB data cache
— 2 KB “mini” data cache
— Extensive data buffering
256 Kbytes of internal SRAM for high
speed code or data storage preserved
during low-power states
High-speed baseband processor interface
(Mobile Scalable Link)
Rich serial peripheral set:
— AC’97 audio port
— I2S audio port
— USB Client controller
— USB Host controller
— USB On-The-Go controller
— Three high-speed UARTs (two with
hardware flow control)
— FIR and SIR infrared communications
port
Hardware debug features — IEEE JTAG
interface with boundary scan
Hardware performance-monitoring
features with on-chip trace buffer
Real-time clock
w Operating-system timers
w LCD Controller
w Universal Subscriber Identity Module
.DataSheet4U.cominterface
Low power:
— Wireless Intel Speedstep® Technology
— Less than 500 mW typical internal
dissipation
— Supply voltage may be reduced to
0.85 V
— Four low-power modes
— Dynamic voltage and frequency
management
High-performance memory controller:
— Four banks of SDRAM: up to 104 MHz
@ 2.5V, 3.0V, and 3.3V I/O interface
— Six static chip selects
— Support for PCMCIA and Compact
Flash
— Companion chip interface
Flexible clocking:
— CPU clock from 104 to 624 MHz
— Flexible memory clock ratios
— Frequency changes
— Functional clock gating
Additional peripherals for system
connectivity:
— SD Card / MMC Controller (with SPI
mode support)
— Memory Stick card controller
— Three SSP controllers
— Two I2C controllers
— Four pulse-width modulators (PWMs)
— Keypad interface with both direct and
matrix keys support
— Most peripheral pins double as GPIOs
Order Number 280002-005




NHPXA270 pdf, 반도체, 판매, 대치품
Intel® PXA270 Processor
Contents
6.2.7 Standby-Mode Timing .................................................................6-10
6.2.8 Idle-Mode Timing.........................................................................6-10
6.2.9 Frequency-Change Timing..........................................................6-10
6.2.10 Voltage-Change Timing...............................................................6-11
6.3 GPIO Timing Specifications .....................................................................6-11
6.4 Memory and Expansion-Card Timing Specifications................................6-12
6.4.1 Internal SRAM Read/Write Timing Specifications .......................6-12
6.4.2 SDRAM Parameters and Timing Diagrams.................................6-12
6.4.3 ROM Parameters and Timing Diagrams .....................................6-18
6.4.4 Flash Memory Parameters and Timing Diagrams.......................6-23
6.4.5 SRAM Parameters and Timing Diagrams ...................................6-33
6.4.6 Variable-Latency I/O Parameters and Timing Diagrams.............6-36
6.4.7 Expansion-Card Interface Parameters and Timing Diagrams.....6-40
6.5 LCD Timing Specifications .......................................................................6-43
6.6 SSP Timing Specifications .......................................................................6-44
6.7 JTAG Boundary Scan Timing Specifications............................................6-45
Figures
2-1 Intel® PXA270 Processor Block Diagram, Typical System................................2-2
3-1 13x13mm VF-BGA Intel® PXA270 Processor Package, top view .....................3-1
3-2 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-2
3-3 13x13mm VF-BGA Intel® PXA270 Processor Package, side view ...................3-3
3-4 VF-BGA Product Information Decoder...............................................................3-3
3-5 23x23 mm PBGA Intel® PXA270 Processor Package (Top View) ....................3-4
3-6 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View) ...............3-4
3-7 23x23 mm PBGA Intel® PXA270 Processor Package (Side View) ...................3-5
3-8 PBGA Product Information Decoder ..................................................................3-5
3-9 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-6
3-10Intel® PXA270 Processor Production Markings, (Laser Mark on Top Side)......3-7
4-1 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) .............................4-2
4-2 13x13 mm VF-BGA Ball Map, Top View (upper right quarter) ...........................4-3
4-3 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) ...........................4-4
4-4 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) ........................4-5
4-5 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter) ..............................4-6
4-6 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter)............................4-7
4-7 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) ..............................4-8
4-8 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)............................4-9
6-1 AC Test Load .....................................................................................................6-2
6-2 Power On Reset Timing .....................................................................................6-3
6-3 Hardware Reset Timing .....................................................................................6-4
6-4 GPIO Reset Timing ............................................................................................6-5
6-5 Sleep Mode Timing ............................................................................................6-7
6-6 Deep-Sleep-Mode Timing ..................................................................................6-8
6-7 SDRAM Timing ................................................................................................6-15
6-8 SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing............................6-16
6-9 SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing ...............6-17
6-10SDRAM Fly-by DMA Timing.............................................................................6-18
6-1132-Bit Non-burst ROM, SRAM, or Flash Read Timing .....................................6-20
iv Electrical, Mechanical, and Thermal Specification

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NHPXA270 전자부품, 판매, 대치품
Revision History
Intel® PXA270 Processor
Contents
Date
April 2004
June 2004
June 2004
October 2004
April 2005
Revision
-001
-002
-003
-004
-005
Description
First public release of the EMTS
Added 23x23 mm 360-ball PBGA package
Added 624-MHz active and idle power consumption values to
Table 5-7.
Modified Power Consumption introduction in Chapter 5, “Power-
Consumption Specifications”
Modified Watchdog Reset timing description Chapter 6, “Reset
and Power Manager Timing Specifications”
Corrected 13 MHz Oscillator slew rate specification Section 5.5,
“Oscillator Electrical Specifications”
Added note to VCC_BB voltage specifications, Chapter 5,
“Electrical Specifications”
Modified Core Voltage and Frequency Electrial Specifications,
Chapter 5, “Electrical Specifications”
Modified SDRAM Parameters and Timing Diagrams, Chapter 6,
“AC Timing Specifications”
Modified Processor Material Properties,Chapter 3, “Package
Information”
§§
Electrical, Mechanical, and Thermal Specification
vii

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