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부품번호 AD6650 기능
기능 Diversity IF to Baseband GSM/EDGE Narrowband Receiver
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AD6650 데이터시트, 핀배열, 회로
AD6650 Diversity IF-to-Baseband
GSM/EDGE Narrow-Band Receiver
AD6650
FEATURES
116 dB dynamic range
Digital VGA
I/Q demodulators
Active low-pass filters
Dual wideband ADC
Programmable decimation and channel filters
VCO and phase-locked loop circuitry
Serial data output ports
Intermediate frequencies of 70 MHz to 260 MHz
10 dB noise figure
+43 dBm input IP2 at 70 MHz IF
−9.5 dBm input IP3 at 70 MHz IF
3.3 V I/O and CMOS core
Microprocessor interface
JTAG boundary scan
APPLICATIONS
PHS or GSM/EDGE single carrier, diversity receivers
Microcell and picocell systems
Wireless local loop
Smart antenna systems
Software radios
In-building wireless telephony
PRODUCT DESCRIPTION
The AD6650 is a diversity intermediate frequency-to-baseband
(IF-to-baseband) receiver for GSM/EDGE. This narrow-band
receiver consists of an integrated DVGA, IF-to-baseband I/Q
demodulators, low-pass filtering, and a dual wideband ADC.
The chip can accommodate IF input from 70 MHz to 260 MHz.
The receiver architecture is designed such that only one external
surface acoustic wave (SAW) filter for main and one for diversity
are required in the entire receive signal path to meet GSM/EDGE
blocking requirements.
Digital decimation and filtering circuitry provided on-chip
remove unwanted signals and noise outside the channel of
interest. Programmable RAM coefficient filters allow antialiasing,
matched filtering, and static equalization functions to be combined
in a single cost-effective filter. The output of the channel filters
is provided to the user via serial output I/Q data streams.
AIN
VGA
AIN
CPOUT
LF
VLDO
PLL/
VCO
BIN
VGA
BIN
0
/4 90
FUNCTIONAL BLOCK DIAGRAM
TWEAK GAIN
DAC
I
LPF
MUX
LPF
Q
AGC
RELIN
CTRL
12-BIT
ADC
COARSE
DCC
LP
FILTER
4TH
ORDER
CIC
7TH
ORDER
IIR
REF
LPF
LPF
JTAG
Q
MUX
12-BIT
ADC
COARSE
DCC
I
DAC
TWEAK GAIN
CLK
DIVIDER
AGC
RELIN
CTRL
4TH
ORDER
CIC
7TH
ORDER
IIR
LP
FILTER
AD6650 GSM/
EDGE IF RECEIVER
PROG.
FIR
(RCF)
FINE
DCC
BIST
SERIAL
PORT
SCLK
SDFS
SDO0
SDO1
DR
PROG.
FIR
(RCF)
FINE
DCC
BIST
MICRO
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.




AD6650 pdf, 반도체, 판매, 대치품
AD6650
SPECIFICATIONS
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C; sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter guaranteed by design and analysis.
V. Parameter is typical value only.
VI. 100% production tested at 25°C; sample tested at temperature extreme.
VII. 100% production tested at +85°C.
CLOAD = 40 pF on all outputs, unless otherwise specified. All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO
range of 3.0 V to 3.45 V.
AC SPECIFICATIONS
AVDD and DVDD = 3.3 V, CLK = 52 MSPS (driven differentially), 50% duty cycle, unless otherwise noted. All minimum ac
specifications are guaranteed from −25°C to +85°C. AC minimum specifications degrade slightly from −25°C to −40°C.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
GAIN CONTROL
Gain Step Size
Gain Step Accuracy
AGC Range
BASEBAND FILTERS
Bandwidth
Alias Rejection at 25.9 MHz
LO PHASE NOISE
At 10 kHz Offset
At 20 kHz Offset
At 50 kHz Offset
At 100 kHz Offset
At 200 kHz Offset
At 400 kHz Offset
At 600 kHz Offset
At 800 kHz Offset
At 1600 kHz Offset
At 3000 kHz Offset
GAIN ERROR
PSRR (AVDD with 20 mV RMS Ripple)1
At 5 kHz
At 10 kHz
At 50 kHz
At 100 kHz
At 150 kHz
f = 70 MHz
Coarse DC Correction
Noise Figure2
Input IP22
Input IP32
Image Rejection
Full-Scale Input Power
Input Impedance
Temp
Test Level
Full V
25°C V
25°C V
25°C V
Full IV
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
V
V
Full IV
Full IV
Full IV
V
V
Rev. A | Page 3 of 44
Min Typ
70
0.094
±0.047
36
3.36 3.5
77
−79
−87
−103
−112
−119
−125
−130
−133
−138
−143
−0.7
−13.4
−17
−34
−39.8
−45.7
−70
10
24 43
−15 −9.5
−49
4
189.6 − j33.6
Max Unit
260 MHz
dB
dB
dB
3.64 MHz
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dB
dBc
dBc
dBc
dBc
dBc
dB
dB
dBm
dBm
−33 dBc
dBm
Ω

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AD6650 전자부품, 판매, 대치품
AD6650
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.
Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation
Parameter
Symbol Temp Test Level
WRITE TIMING
WR (R/W) to RDY (DTACK) Hold Time1
tHWR Full
IV
Address/Data to WR (R/W) Setup Time1
tSAM Full IV
Address/Data to RDY (DTACK) Hold Time1
tHAM Full
IV
WR (R/W) to RDY (DTACK) Delay
tDRDY 2
Full
IV
WR (R/W) to RDY (DTACK) High Delay1
tACC Full IV
READ TIMING
Address to RD (DS) Setup Time1
tSAM Full IV
Address to Data Hold Time1
Data Three-state Delay1
RDY (DTACK) to Data Delay1
tHAM Full
tZD Full
tDD Full
IV
V
IV
RD (DS) to RDY (DTACK) Delay
tDRDY2
Full
IV
RD (DS) to RDY (DTACK) High Delay1
tACC Full IV
Min
0.0
0.0
0.0
9.0
4 × tCLK
0.0
0.0
9.0
4 × tCLK
Typ Max
15.0
13 × tCLK
12
0.0
15.0
13 × tCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Timing is guaranteed by design.
2 Specification pertains to control signals R/W, WR, DS, RD, and CS such that the minimum specification is valid after the last control signal has reached a valid logic level.
Table 6. Microprocessor Port, Mode MNM (MODE = 1)
Parameter
Symbol
WRITE TIMING
DS (RD) to DTACK (RDY) Hold Time
tHDS
R/W (WR) to DTACK (RDY) Hold Time
tHRW
Address/Data to R/W (WR) Setup Time1
tSAM
Address/Data to R/W (WR) Hold Time1
tHAM
DS (RD) to DTACK (RDY) Delay2
tDDTACK
R/W (WR) to DTACK (RDY) Low Delay1
tACC
READ TIMING
DS (RD) to DTACK (RDY) Hold Time
tHDS
Address to DS (RD) Setup Time1
tSAM
Address to Data Hold Time1
tHAM
Data Three-State Delay
DTACK (RDY) to Data Delay1
tZD
tDD
DS (RD) to DTACK (RDY) Delay2
tDDTACK
DS (RD) to DTACK (RDY) Low Delay1
tACC
1 Timing is guaranteed by design.
2 DTACK is an open-drain device and must be pulled up with a 1 kΩ resistor.
Temp Test Level
Full IV
Full IV
Full IV
Full IV
Full V
Full IV
Full IV
Full IV
Full IV
Full V
Full IV
Full V
Full IV
Min
15.0
15.0
0.0
0.0
4 × tCLK
15.0
0.0
0.0
4 × tCLK
Typ Max
16
13 × tCLK
13
0.0
16
13 × tCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 6 of 44

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