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부품번호 AD6652 기능
기능 12-Bit / 65 MSPS IF to Baseband Diversity Receiver
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AD6652 데이터시트, 핀배열, 회로
12-Bit, 65 MSPS
IF to Baseband Diversity Receiver
AD6652
FEATURES
SNR = 90 dB in 150 kHz bandwidth (to Nyquist
@ 61.44 MSPS)
Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
Integrated dual-channel ADC:
Sample rates up to 65 MSPS
IF sampling frequencies to 200 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range (1 V to 2 V p-p)
Differential analog inputs
ADC clock duty cycle stabilizer
85 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC):
Crossbar switched DDC inputs
Digital resampling for noninteger decimation
Programmable decimating FIR filters
Flexible control for multicarrier and phased array
Dual AGC stages for output level control
Dual 16-bit parallel or 8-bit link output ports
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,
IS95, IS136, CDMA2000, IMT-2000
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM
DUAL-CHANNEL 12-BIT A/D FRONT END
WIDEBAND DIGITAL DOWNCONVERTER (DDC)
VINA+
VINA–
SHA
REFTA
REFBA
VREF
SENSE
REFTB
REFBB
VINB+
VINB–
SHA
ADC 12 CHANNEL A
CHANNEL /
A
OTRA
LIA
LIA
VREF
PSEUDO
RANDOM
NOISE
SEQUENCE
LIB
LIB
OTRB
ADC 12
CHANNEL /
B CHANNEL B
RCIC2
RESAMPLER
CIC5
NCO
RCIC2
RESAMPLER
CIC5
NCO
RCIC2
RESAMPLER
CIC5
NCO
RCIC2
RESAMPLER
CIC5
NCO
RAM
COEF.
FILTER
CHANNEL 0
RAM
COEF.
FILTER
CHANNEL 1
RAM
COEF.
FILTER
CHANNEL 2
RAM
COEF.
FILTER
CHANNEL 3
TO OUTPUT PORTS
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
TO OUTPUT PORTS
AGC A*
TO OUTPUT
PORTS
AGC B*
TO OUTPUT PORTS
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
PORT A
8-BIT DSP
LINK
OR
16-BIT
PARALLEL
OUTPUT
CONTROL
OUTPUT
MUX
CIRCUITRY
PORT B
8-BIT DSP
LINK
OR
16-BIT
PARALLEL
OUTPUT
PDWN
SHRDREF
MODE ACLK
SELECT DUTYEN
CLOCK
DUTY
CYCLE
STABILIZER
SYNCA
SYNCB
SYNCC
SYNCD
EXTERNAL
SYNC.
CIRCUIT
*DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL
DDC
CLK
BUILT-IN
SELF-TEST
CIRCUITRY
PROGRAM
MICROPORT
8 33
+3.0AVDD
+3.3VDDIO
2.5VDD
AGND
DGND
CLK
DATA CONT ADD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD6652 pdf, 반도체, 판매, 대치품
AD6652
PRODUCT DESCRIPTION
The AD6652 is a mixed-signal IF to baseband receiver
consisting of dual 12-bit 65 MSPS ADCs and a wideband
multimode digital downconverter (DDC). The AD6652 is
designed to support communications applications where low
cost, small size, and versatility are desired. The AD6652 is also
suitable for other applications in imaging, medical ultrasound,
instrumentation, and test equipment.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Both
ADCs feature wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compen-
sate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
ADC data outputs are internally connected directly to the
receiver’s digital downconverter (DDC) input matrix, simplify-
ing layout and reducing interconnection parasitics. Overrange
bits are provided for each ADC channel to alert the user to
ADC clipping. Level indicator bits are also provided for each
DDC input port that can be used for external digital VGA
control.
The digital receiver has four reconfigurable channels and
provides extraordinary processing flexibility. The receiver input
matrix routes the ADC data to individual channels, or to all four
receive processing channels. Each receive channel has five
cascaded signal processing stages: a 32-bit frequency translator
(numerically controlled oscillator (NCO)), two fixed-coefficient
decimating filters (CIC), a programmable RAM coefficient
decimating FIR filter (RCF), and an interpolating half-band
filter/AGC stage. Following the CIC filters, one, several, or all
channels can be configured to use one, several, or all the RCF
filters. This permits the processing power of four 160-tap RCF
FIR filters to be combined or used individually.
After FIR filtering, data can be routed directly to the two
external 16-bit output ports. Alternatively, data can be routed
through two additional half-band interpolation stages, where up
to four channels can be combined (interleaved), interpolated,
and processed by an automatic gain control (AGC) circuit with
96 dB range. The outputs from the two AGC stages are also
routed directly to the two external 16-bit output ports. Each
output port has a 16-bit parallel output and an 8-bit link port to
permit seamless data interface with DSP devices such as the
TS-101 TigerSHARC® DSP. A multiplexer for each port selects
one of six data sources to appear on the device outputs pins.
The AD6652 is part of the Analog Devices SoftCell® multimode
and multicarrier transceiver chipset. The SoftCell receiver
digitizes a wide spectrum of IF frequencies and then down-
converts the desired signals to baseband using individual
channel NCOs. The AD6652 provides user-configurable digital
filters for removal of undesired baseband components, and the
data is then passed on to an external DSP, where demodulation
and other signal processing tasks are performed to complete the
information retrieval process. Each receive channel is independ-
ently configurable to provide simultaneous reception of the
carrier to which it is tuned. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications. The decimating
filters remove unwanted signals and noise from the channel of
interest. When the channel occupies less bandwidth than the
input signal, this rejection of out-of-band noise is referred to as
processing gain. By using large decimation factors, this process-
ing gain can improve the SNR of the ADC by 20 dB or more. In
addition, the programmable RAM coefficient filter allows
antialiasing, matched filtering, and static equalization functions
to be combined in a single, cost-effective filter.
Flexible power-down options allow significant power savings,
when desired.
PRODUCT HIGHLIGHTS
Integrated dual 12-bit 65 MSPS ADC.
Integrated wideband digital downconverter (DDC).
Proprietary, differential SHA input maintains excellent
SNR performance for input frequencies up to 200 MHz.
Crossbar-switched digital downconverter input ports.
Digital resampling permits noninteger relationships
between the ADC clock and the digital output data rate.
Energy-saving power-down modes.
32-bit NCOs with selectable amplitude and phase dithering
for better than −100 dBc spurious performance.
CIC filters with user-programmable decimation and
interpolation factors.
160-tap RAM coefficient filter for each DDC channel.
Dual 16-bit parallel output ports and dual 8-bit link ports.
8-bit microport for register programming, register read-
back, and coefficient memory programming.
Rev. 0 | Page 4 of 76

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AD6652 전자부품, 판매, 대치품
AD6652
ELECTRICAL CHARACTERISTICS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 5.
Parameter (Conditions)
LOGIC INPUTS
Logic Compatibility
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
LOGIC OUTPUTS
Logic Compatibility
Logic 1 Voltage (VOH) (IOH = 0.25 mA)
Logic 0 Voltage (VOL) (IOL = 0.25 mA)
SUPPLY CURRENTS
Narrow Band (150 kHz BW) (61.44 MHz CLK)
Four Individual Channels
IAVDD
IVDD
IVDDIO
CDMA (1.25MHz BW) (61.44 MHz CLK) Example1
IAVDD
IVDD
IVDDIO
WCDMA (5 MHz BW) (61.44 MHz CLK) Example1
IAVDD
IVDD
IVDDIO
TOTAL POWER DISSIPATION
Narrow Band (150 kHz BW) (61.44 MHz CLK)
Four Individual Channels
CDMA (61.44 MHz)1
Temp Test Level Min
Full IV
Full IV
Full IV
Full IV
Full IV
25°C V
2.0
−10
−10
Full IV
Full IV
Full IV
2.4
25°C II
25°C II
25°C II
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C II
25°C V
160
240
25
1.2
Typ Max Unit
3.3 V CMOS
4
V
0.8 V
+10 µA
+10 µA
pF
3.3 V CMOS/TTL
VDDIO − 0.2
0.2
0.4
V
V
200 215 mA
280 300 mA
40 45 mA
200 mA
336 mA
68 mA
200 mA
330 mA
89 mA
1.5 1.6 W
1.7 W
WCDMA (61.44 MHz)1
25°C V
1.7 W
ADC in Standby and DDC in Sleep Mode2
25°C V
2.3 mW
1 All signal processing stages and all DDC channels active.
2 ADC standby power measured with ACLK inactive.
Rev. 0 | Page 7 of 76

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