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PDF PM25LV010 Data sheet ( Hoja de datos )
| Número de pieza | PM25LV010 | |
| Descripción | (PM25LV010 / PM25LV512) Serial Flash Memory | |
| Fabricantes | Programmable Microelectronics | |
| Logotipo |  |
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PMC
Pm25LV512 / Pm25LV010
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory
With 25 MHz SPI Bus Interface
FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
Block Write Protection
- The Block Protect (BP1, BP0) bits allow part or entire
of the memory to be configured as read-only.
• Memory Organization
- Pm25LV512: 64K x 8 (512 Kbit)
Hardware Data Protection
- Pm25LV010: 128K x 8 (1 Mbit)
- Write Protect (WP#) pin will inhibit write operations
to the status register
Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
m- Uniform 32 Kbyte blocks (8 sectors per block)
o- Two blocks with 32 Kbytes each (512 Kbit)
- Four blocks with 32 Kbytes each (1 Mbit)
.c- 128 pages per block
Serial Peripheral Interface (SPI) Compatible
U- Supports SPI Modes 0 (0,0) and 3 (1,1)
t4 High Performance Read
- 25 MHz clock rate (maximum)
e Page Mode for Program Operations
She- 256 bytes per page
• Page Program (up to 256 Bytes)
- Typical 2 ms per page program time
• Sector, Block and Chip Erase
- Typical 40 ms sector/block/chip erase time
Single Cycle Reprogramming for Status Register
- Build-in erase before programming
High Product Endurance
- Guarantee 100,000 program/erase cycles per single
sector (preliminary)
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin JEDEC SOIC
- 8-contact WSON
- Optional lead-free (Pb-free) packages
taGENERAL DESCRIPTION
aThe Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use
.Da single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations.
The devices can be programmed in standard EPROM programmers as well.
wThe device is optimized for use in many commercial applications where low-power and low-voltage operation are
essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface
wconsisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are com-
wpletely self-timed.
Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled
by programming the status register. Separate write enable and write disable instructions are provided for additional
data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts
to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial
sequence.
The Pm25LV512/010 are manufactured on PMC’s advanced nonvolatile CMOS technology, P-FLASH™. The de-
vices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
Programmable Microelectronics Corp. 1 Issue Date: February, 2004, Rev: 1.4
1 page  
PMC
Pm25LV512/010
SERIAL INTERFACE DESCRIPTION
Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication
term definitions are in the following section.
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave.
TRANSMITTER/RECEIVER: The Pm25LV512/010 has separate pins designated for data transmission (SO) and
reception (Sl).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CE# going low, the first byte will be received. This byte
contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the Pm25LV512/010, and the serial
output pin (SO) will remain in a high impedance state until the falling edge of CE# is detected again. This will
reinitialize the serial communication.
Figure 1. Bus Master and SPI Memory Devices
SPI Interface with
(0, 0) or (1, 1)
Bus Master
CS3 CS2 CS1
SDO
SDI
SCK
SCK SO SI
SPI Memory
Device
SCK SO SI
SPI Memory
Device
SCK SO SI
SPI Memory
Device
CE#
WP# HOLD# CE#
WP# HOLD# CE#
WP# HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
Programmable Microelectronics Corp.
5
Issue Date: February, 2004, Rev: 1.4
5 Page 
PMC
Pm25LV512/010
SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the
byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the
device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction
can be executed.
Table 8. Block Addresses
Block Address
000000 to 007FFF
008000 to 00FFFF
010000 to 017FFF
018000 to 01FFFF
Pm25LV512 Block
Block 1
Block 2
N/A
N/A
Pm25LV010 Block
Block 1
Block 2
Block 3
Block 4
The BLOCK ERASE instruction erases every byte in the selected block if the block is not locked out. Block
address is automatically determined if any address within the block is selected. The BLOCK ERASE instruction
is internally controlled; it will automatically be timed to completion. During this time, all commands will be ignored,
except RDSR instruction. The Pm25LV512/010 will automatically return to the write disable state at the completion
of the BLOCK ERASE cycle.
CHIP_ERASE: As an alternative to the SECTOR and BLOCK ERASE, the CHIP ERASE instruction will erase
every byte in all blocks that are not locked out. First, the device must be write enabled via the WREN instruction.
Then the CHIP ERASE instruction can be executed. The CHIP ERASE instruction is internally controlled; it will
automatically be timed to completion. The CHIP ERASE cycle time maximum is 100 miliseconds. During the
internal erase cycle, all instructions will be ignored except RDSR. The Pm25LV512/010 will automatically return to
the write disable state at the completion of the CHIP ERASE.
HOLD: The HOLD# pin is used in conjunction with the CE# pin to select the Pm25LV512/010. When the device is
selected and a serial sequence is underway, HOLD# pin can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD# pin must be brought low while the SCK
pin is low. To resume serial communication, the HOLD# pin is brought high while the SCK pin is low (SCK may still
toggle during HOLD). Inputs to the Sl pin will be ignored while the SO pin is in the high impedance state.
HARDWARE WRITE PROTECT: The Pm25LV512/010 has a write lockout feature that can be activated by assert-
ing the write protect pin (WP#). When the lockout feature is activated, locked-out sectors will be READ only. The
write protect pin will allow normal read/write operations when held high. When the WP# is brought low and WPEN
bit is "1", all write operations to the status register are inhibited. WP# going low while CE# is still low will interrupt
a write to the status register. If the internal status register write cycle has already been initiated, WP# going low will
have no effect on any write operation to the status register. The WP# pin function is blocked when the WPEN bit in
the status register is "0". This will allow the user to install the Pm25LV512/010 in a system with the WP# pin tied
to ground and still be able to write to the status register. All WP# pin functions are enabled when the WPEN bit is
set to "1".
Programmable Microelectronics Corp.
11
Issue Date: February, 2004, Rev: 1.4
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PM25LV010.PDF ] | |
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