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KM29U64000T 데이터시트 PDF




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부품번호 KM29U64000T 기능
기능 8M x 8 Bit NAND Flash Memory
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KM29U64000T 데이터시트, 핀배열, 회로
KM29U64000T, KM29U64000IT
Document Title
8M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 Data Sheet, 1998
1.1 Data Sheet. 1999
1) Added CE dont’ care mode during the data-loading and reading
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
Remark
Preliminary
Final
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the
SAMSUNG branch office near you.
1




KM29U64000T pdf, 반도체, 판매, 대치품
KM29U64000T, KM29U64000IT
FLASH MEMORY
PRODUCT INTRODUCTION
The KM29U64000 is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16
pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29U64000.
The KM29U64000 has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29U64000.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Sequential Data Input
80h
-
Read 1
00h/01h(1)
-
Read 2
50h(2)
-
Read ID
90h -
Reset
FFh -
O
Page Program
10h -
Block Erase
60h D0h
Read Status
70h -
O
NOTE : 1. The 00H command defines starting address of the 1st half of registers.
The 01H command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the SE(pin 40) is low level.
4

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KM29U64000T 전자부품, 판매, 대치품
KM29U64000T, KM29U64000IT
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
1014
Typ.
1020
Max
1024
Unit
Blocks
NOTE :
1. The KM29U64000 may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid
blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaran-
teed though its initial number could be reduced. (Refer to the attached technical notes)
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(KM29U64000T:TA=0 to 70°C, KM29U64000IT:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load (3.0V +/-10%)
1 TTL GATE and CL = 50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE
WE
RE
SE
WP
Mode
HL L
LHL
HXX
Command Input
Read Mode
HXX
Address Input(3clock)
HL L
LHL
HXH
Command Input
Write Mode
HXH
Address Input(3clock)
LLL
H L/H(3) H Data Input
L L LH
L/H(3)
X Sequential Read & Data Output
L L L H H L/H(3) X During Read(Busy)
X X X X X L/H(3) H During Program(Busy)
X X X X X X H During Erase(Busy)
X X(1) X X X X L Write Protect
X X H X X 0V/VCC(2) 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
3. When SE is high, spare area is deselected.
Program/Erase Characteristics
Parameter
Program Time
Number of Partial Program Cycles in the Same Page
Block Erase Time
Symbol
tPROG
Nop
tBERS
Min
-
-
-
Typ Max
200 1000
- 10
24
Unit
µs
cycles
ms
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관련 데이터시트

부품번호상세설명 및 기능제조사
KM29U64000IT

8M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor
KM29U64000T

8M x 8 Bit NAND Flash Memory

Samsung semiconductor
Samsung semiconductor

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