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89C51RD2 데이터시트 PDF




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89C51RD2 데이터시트, 핀배열, 회로
T89C51RD2
0 to 40MHz Flash Programmable 8-bit Microcontroller
1. Description
ATMEL Wireless and Microcontrollers T89C51RD2 is
high performance CMOS Flash version of the 80C51
CMOS single chip 8-bit microcontroller. It contains a
64 Kbytes Flash memory block for program and for data.
The 64 Kbytes Flash memory can be programmed either
in parallel mode or in serial mode with the ISP capability
or with software. The programming voltage is internally
generated from the standard VCC pin.
The T89C51RD2 retains all features of the ATMEL
Wireless and Microcontrollers 80C52 with 256 bytes of
www.DataShineteetr4nUa.lcoRmAM, a 7-source 4-level interrupt controller and
three timer/counters.
In addition, the T89C51RD2 has a Programmable
Counter Array, an XRAM of 1024 bytes, an EEPROM
of 2048 bytes, a Hardware Watchdog Timer, a more
versatile serial channel that facilitates multiprocessor
communication (EUART) and a speed improvement
mechanism (X2 mode). Pinout is either the standard 40/
44 pins of the C52 or an extended version with 6 ports
in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T89C51RD2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
The added features of the T89C51RD2 makes it more
powerful for applications that need pulse width
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
2. Features
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports (or 6 in 64/68 pins packages)
Three 16-bit timer/counters
256 bytes scratch pad RAM
7 Interrupt sources with 4 priority levels
ISP (In System Programming) using standard VCC
power supply.
Boot FLASH contains low level FLASH
programming routines and a default serial loader
High-Speed Architecture
40 MHz in standard mode
20 MHz in X2 mode (6 clocks/machine cycle)
64K bytes on-chip Flash program / data Memory
Byte and page (128 bytes) erase and write
10k write cycles
On-chip 1024 bytes expanded RAM (XRAM)
Software selectable size (0, 256, 512, 768, 1024
bytes)
768 bytes selected at reset for T87C51RD2
compatibility
Dual Data Pointer
Variable length MOVX for slow RAM/peripherals
Improved X2 mode with independant selection for
CPU and each peripheral
2 k bytes EEPROM block for data storage
100K Write cycle
Programmable Counter Array with:
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
Asynchronous port reset
Full duplex Enhanced UART
Low EMI (inhibit ALE)
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
Power control modes:
Idle Mode.
Power-down mode.
Rev. F - 15 February, 2001
1




89C51RD2 pdf, 반도체, 판매, 대치품
T89C51RD2
reserved
www.DataSheet4U.com
4 Rev. F - 15 February, 2001

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89C51RD2 전자부품, 판매, 대치품
T89C51RD2
Mnemonic
VSS
Vss1
VCC
P0.0-P0.7
P1.0-P1.7
www.DataSheet4U.com
P2.0-P2.7
P3.0-P3.7
Pin Number
DIL LCC VQFP 1.4
20 22
16
1 39
40 44
38
39-32 43-36 37-30
1-8 2-9
40-44
1-3
12
23
34
45
56
67
78
89
21-28 24-31
40
41
42
43
44
1
2
3
18-25
10-17 11,
13-19
5,
7-13
10 11
11 13
12 14
13 15
14 16
15 17
16 18
5
7
8
9
10
11
12
Type Name and Function
I Ground: 0V reference
I Optional Ground: Contact the Sales Office for ground connection.
I
Power Supply: This is the power supply voltage for normal, idle and power-
down operation
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 must be
polarized to VCC or VSS in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Port 1 also receives the low-order address
byte during memory programming and verification.
Alternate functions for TSC8x54/58 Port 1 include:
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
I ECI (P1.2): External Clock for the PCA
I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
I/O CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification:
P2.0 to P2.5 for RB devices
P2.0 to P2.6 for RC devices
P2.0 to P2.7 for RD devices.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves the special features
of the 80C51 family, as listed below.
I RXD (P3.0): Serial input port
O TXD (P3.1): Serial output port
I INT0 (P3.2): External interrupt 0
I INT1 (P3.3): External interrupt 1
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
Rev. F - 15 February, 2001
7

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