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PDF MST8011A Data sheet ( Hoja de datos )
| Número de pieza | MST8011A | |
| Descripción | XGA LCD Controller | |
| Fabricantes | MSTAR | |
| Logotipo |  |
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MST8011A
XGA LCD Controller with Analog Interface and Single LVDS Transmitter
Preliminary Data Sheet Version 0.1
FEATURES
Ÿ High-quality zoom and shrink scaling engine
mode (all VESA & IBM modes w/ resolution
(Compatible with VGA thru XGA)
and polarity) detection
Ÿ Integrated 8-bit triple-ADC/PLL
Ÿ Auto-tuning function including phasing,
Ÿ On-screen display controller (OSD)
positioning, offset, gain, and jitter detection
Ÿ Supports single-RGB inputs
Ÿ Smart screen-fitting
Ÿ Supports composite sync and SOG separator
n On-Screen OSD Controller
Ÿ Programmable 10-bit gamma correction
Ÿ Built-in OSD generator with 256 character font
Ÿ Integrated Brightness & Contrast control
programmable RAM
adjustment
Ÿ Supports for 4/8 multi-color fonts
Ÿ Supports PWM backlit intensity control
Ÿ Supports sRGB
Ÿ Green PC and low EMI features
mŸ Built-in LVDS transmitter
oŸ Low standby power mode (< 15mA)
n High-Performance Scaling Engine
.cŸ Programmable shrink/zoom capabilities
Ÿ High-quality scaling for all VESA and IBM mode
to fit screen
UŸ Variable sharpness control
n Analog RGB Compliant Input Port
t4Ÿ Supports up to XGA at 85Hz
Ÿ Supports Composite Sync and SOG
e(Sync-on-Green) separator
n Auto-Detection/Tune
eŸ Auto input signal format (SOG, Composite,
hSeparated HSYNC, VSYNC, and DE), and input
SBLOCK DIAGRAM
Ÿ Gradient color function
Ÿ Supports button function
Ÿ Pattern generator for production test
Ÿ Support OSD MUX and alpha blending
capability
n LVDS Display Interface
Ÿ Supports Single Link up to 85MHz dot clock for
XGA
Ÿ Supports 2 data output formats: Thine & TI
data mappings
Ÿ Compatible with TIA/EIA
Ÿ With 6/8 bits options
Ÿ Reduced swing for LVDS for low EMI
n External Connection/Component
Ÿ Built-in DDC circuit
Ÿ Supports serial (up to 400Kbit/sec) bus type
ataAnalog
RGB
.DAnalog
wwwHSYNC
ADC
ADC_PLL
HOST
interface
Scaling
Engine
OSD SSC
LVDS
To Panel
MCU
GENERAL DESCRIPTION
XTAL/EXT CLK
The MST8011A is a high performance, and fully integrated graphics processing IC solution for LCD monitors
with resolutions up to XGA. It is configured with an integrated triple-ADC/PLL, a high quality scaling engine,
an on-screen display controller, a built-in output clock generator, and LVDS display interface. To further
reduce system costs, the MST8011A also integrates intelligent power management control capability for
.comgreen-mode requirements and spread-spectrum support for EMI management.
www.DataSheet4UVersion 0.1
-1-
Copyright © 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
1 page  
MST8011A
XGA LCD Controller with Analog Interface and Single LVDS Transmitter
Preliminary Data Sheet Version 0.1
ELECTRICAL SPECIFICATIONS
Analog Interface Characteristics
Parameter
Resolution
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Input Bias Current
Input Full-Scale Matching
Brightness Level Adjustment
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
HSYNC Input Frequency
PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Channel to Channel Matching
Specifications subject to change without notice.
Min
1.0
165
15
20
2.5
VDDP-0.1
Typ
8
±0.5
±1
Guaranteed
Max
+1.25/-1.0
0.5
1
1.5
62
20
200
162.5
500
TBD
0.8
-1.0
1.0
5
250
0.5%
0.1
Unit
Bits
LSB
LSB
V p-p
V p-p
uA
%FS
%FS
MSPS
MSPS
kHz
MHz
ps p-p
ps/°C
V
V
uA
uA
pF
V
V
MHz
Full-Scale
Version 0.1
-5-
Copyright © 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
5 Page 
Ÿ1
n BMID
Ÿ0
Ÿ1
n OFIR
Ÿ0
Ÿ1
n SOG_LVL[4:0]
n ADCBW[2:0]
Ÿ 000
Ÿ 001
Ÿ 010
Ÿ 011
Ÿ 111
n CLPF
Ÿ0
Ÿ1
n XSEL
Ÿ0
Ÿ1
n HS_LVL[2:0]
MST8011A
XGA LCD Controller with Analog Interface and Single LVDS Transmitter
Preliminary Data Sheet Version 0.1
Enable (used when YPbPr input)
Middle clamp of Blue Channel
Disable
Enable (used when YPbPr input)
Output FIR
Disable
Enable (used when YPbPr input)
SOG trigger level
ADC bandwidth
300MHz
150MHz
75MHz
33MHz
15MHz
Clamp Filter
Normal Clamp
Lower current clamp
XTAL Select
Default XTAL
Backup XTAL
HSYNC trigger level
Status
Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
16h
STATUS1
LOCK D7
D6
D5
D4
D3
D2
D1
RO
18h
STATUS5
RCMP[7:0]
RO
19h
STATUS4
PH_STAT[7:0]
RO
1Ah STATUS5 PH_STAT[15:8]
RO
n LOCK
n D7:D1
n RCMP[7:0]
Ÿ
PLL Lock Status
Status
DVI termination resistor status in 2’s complement (DVI feature only)
Positive value represents resistance value on low side, RT_CTL needs to adjust higher
for compensation
Ÿ Negative value represents resistance value on high side, RT_CTL needs to adjust
lower for compensation
n PH_STAT[15:0] DVI phase status indicator in 2’s complement (DVI feature only)
DVI Override (DVI feature only)
Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1Bh DVI_PHR OVPR OVPHR[6:0]
1Ch DVI_PHG OVPG OVPHG[6:0]
1Dh DVI_PHB OVPB OVPHB[6:0]
1Eh DVI_ERST ERR_ST[7:0]
1Fh DVI_ERTH ERR_TH [7:0]
n {OVPR,OVPHR}
n {OVPG,OVPHG}
n {OVPB,OVPHB}
n ERR_ST
n ERR_TH
Freeze & override DVI red channel PLL phase selection with OVPHR[6:0]
Freeze & override DVI green channel PLL phase selection with OVPHG[6:0]
Freeze & override DVI blue channel PLL phase selection with OVPHB[6:0]
DVI bit error status indicator
DVI bit error tolerance threshold
Access
R/W
R/W
R/W
R/W
R/W
Version 0.1
- 11 -
Copyright © 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MST8011A.PDF ] | |
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