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PDF GM5221-LF-BC Data sheet ( Hoja de datos )
| Número de pieza | GM5221-LF-BC | |
| Descripción | Integrated Multimedia LCD Controller | |
| Fabricantes | Genesis Microchip | |
| Logotipo |  |
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Genesis Microchip Publication
PRELIMINARY DATA SHEET
omgm5221-LF-BC
.cIntegrated Multimedia LCD Controller
et4UGENESIS MICROCHIP CONFIDENTIAL
hePublication Number: C5221-DAT-04A
www.DataSPublication Date: March 2004
Genesis Microchip Inc.
www.genesis-microchip.com / [email protected].com
www.DataSheet4U.com
1 page  
gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
List Of Tables
Table 1. Analog Input Port................................................................................................................ 10
Table 2. DVI Input Port .................................................................................................................... 10
Table 3. RCLK PLL Pins.................................................................................................................. 11
Table 4. Input Video Port.................................................................................................................. 11
Table 5. System Interface.................................................................................................................. 12
Table 6. LVDS Display Interface ..................................................................................................... 13
Table 7. TTL Display Interface......................................................................................................... 13
Table 8. RESET Time....................................................................................................................... 20
Table 9. Requirement for RESETn due to Glitch in AVDD_3.3V................................................... 20
Table 10. Pin Connection for RGB Input with HSYNC/VSYNC .................................................. 22
Table 11. ADC Characteristics ....................................................................................................... 23
Table 12. DVI Receiver Characteristics ......................................................................................... 25
Table 13. Supported LVDS 24-bit Panel Data Mappings............................................................... 34
Table 14. Supported LVDS 18-bit Panel Data Mapping ................................................................ 34
Table 15. GPIO and Alternate Functions........................................................................................ 40
Table 16. Bootstrap Signals ............................................................................................................ 41
Table 17. Absolute Maximum Ratings ........................................................................................... 42
Table 18. DC Characteristics .......................................................................................................... 43
Table 19. Maximum Speed of Operation........................................................................................ 44
Table 20. Input Timing for ITU656 Video Port ............................................................................. 44
Table 21. OCM ROM Interface Timing ......................................................................................... 45
C5221-DAT-04A
5
Genesis Microchip Confidential
http://www.genesis-microchip.com
March 2004
5 Page 
gm5221-LF-BC Multimedia LCD Controller Preliminary Data Sheet
Pin Name
RX1-
AVDD_RX1_3.3
VDD_RX0_1.8
AGND_RX0
RX0+
RX0-
AVDD_RX0_3.3
AGND_RXC
RXC+
RXC-
AVDD_RXC_3.3
GND_RXPLL
VDD_RXPLL_1.8
CLK_OUT
Pin Name
GND_RPLL
VDD_RPLL_1.8
AGND_RPLL
XTAL
TCLK
AVDD_RPLL_3.3
Pin Name
VCLK
GPIO23/VDATA0
GPIO22/VDATA1
GPIO21/VDATA2
GPIO20/VDATA3
GPIO19/VDATA4
GPIO18/VDATA5
GPIO17/VDATA6
GPIO16/VDATA7
No I/O Description
124 AI TMDS input pair 1
125 AP Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with to AGND_RX1.
126 AP VDD (1.8V) for TMDS input pair 2. Must be bypassed with external capacitor to GND_RX0.
127 AG Analog GND for TMDS input pair 0. Must be connected directly to the analog ground plane.
128 AI TMDS input pair 0
129 AI TMDS input pair 0
130 AP Analog VDD (3.3V) for TMDS input pair 2. Must be bypassed with capacitor to AGND_RX0.
131 AG Analog GND for TMDS input clock pair. Must be connected directly to the analog ground
plane.
132 AI TMDS input clock pair
133 AI TMDS input clock pair
134 AP Analog VDD (3.3V) for TMDS input clock pair.
Must be bypassed with 100pF capacitor to AGND_RXC.
136 AG Analog GND for the TMDS receiver internal PLL.
Must be connected directly to the analog ground plane.
137 AP Analog VDD (1.8V) for the TMDS receiver internal PLL.
Must be bypassed with a capacitor to AGND_RXPLL.
138 AO Reserved. Leave unconnected.
No
165
166
168
169
170
171
I/O
AG
AP
AG
AO
AI
AP
Table 3. RCLK PLL Pins
Description
Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
plane.
Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to GND1_ADC.
Analog ground for the Reference DDS PLL. Must be directly connected to the analog system
ground plane.
Crystal oscillator output.
Reference clock (TCLK) from the 14.3MHz crystal oscillator.
Analog VDD (3.3V)
Table 4. Input Video Port
No I/O Description
112 I Video port data clock input. Up to 75Mhz
[Input, 5V-tolerant]
111 IO Input YUV data in 8-bit BT656 or GPIO23:16 if VPORT is disabled.
110 [Bi-Directional, 5V-tolerant]
109
108
107
106
103
102
C5221-DAT-04A
11
Genesis Microchip Confidential
http://www.genesis-microchip.com
March 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GM5221-LF-BC.PDF ] | |
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