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부품번호 MC33291 기능
기능 Eight Output Switch with Serial Peripheral Interface I/O
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MC33291 데이터시트, 핀배열, 회로
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33291/D
Rev 2, 11/2002
Eight Output Switch with Serial
Peripheral Interface I/O
The 33291 device is an eight output, low side power switch with 8-bit serial
input control. The 33291 is a versatile circuit designed for automotive applica-
tions, but is well suited for other environments. The 33291 incorporates
SMARTMOStechnology, with CMOS logic, bipolar/MOS analog circuitry,
and DMOS power MOSFETs. The 33291 interfaces directly with a microcon-
troller to control various inductive or incandescent loads.
The circuit’s innovative monitoring and protection features include: Very
Low Standby Current, SPI Cascade Fault Reporting Capability, Internal 53 V
Clamp on Each Output, Output Specific Diagnostics, Independent Shutdown
of Outputs.
The device is parametrically specified over an ambient temperature range
of -40°C TA 125°C and 9.0 V VPWR 16 V supply.
Features:
• Designed to Operate Over Wide Supply Voltages of 5.5 to 26.5 V
• Interfaces to Microprocessor Using 8-Bit SPI I/O Protocol up to 3.0 MHz
• 1.0 A Peak Current Outputs with Maximum RDS(on) of 1.6 at TJ - 150°C
• Outputs Current Limited to Accommodate In-rush Currents Associated
with Switching Incandescent Loads
• Output Voltages Clamped to 53 V During Inductive Switching
• Maximum Sleep Current (IPWR) of 25 µA
• Maximum of 4.0 mA IDD During Operation
33291
EIGHT OUTPUT SWITCH
(SPI I/O)
Package Options
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
SOICW (16+4+4)
ORDERING INFORMATION
Device
Temperature
Range TA
Package
MC33291DW
-40°C to 125°C
SOIC-24
MC33291DWR2 -40°C to 125°C
SOIC-24
33291 Simplified Application Schematic
SFPD
VDD
Micro-
controller
SFPD
CS
SCLK
CMOS
Input
Logic
SI
RST
SO
CMOS
Serial
Shift
Registers
and
Latches
VPWR
Output 0
Output 1
Updrain
DMOS
Output
Switches
and
Sense
Circuits
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
+VBAT
GND
This device contains 1266 active transistors.
© Motorola, Inc. 2002
For More Information On This Product,
Go to: www.freescale.com




MC33291 pdf, 반도체, 판매, 대치품
Freescale Semiconductor, Inc.
MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Power Supply Voltage
Normal Operation (Steady-State)
Transient Conditions (Note 1)
Logic Supply Voltage (Note 2)
Input Pin Voltage (Note 3)
Output Clamp Voltage (Note 4)
5.0 mA Iout 0.5 A
VPWR(SUS)
VPWR(PK)
VDD
VIN
VOUT(OFF)
- 1.5 to 26.5
- 13 to 60
- 0.3 to 7.0
- 0.3 to 7.0
45 to 65
V
V
V
V
Output Self-Limit Current
Continuous Per Output Current (Note 5)
IOUT(LIM)
IOUT(CONT)
1.0 to 3.0
500
A
mA
ESD Voltage (Note 6)
Human Body Model (Note 7)
Machine Model (Note 8)
Output Clamp Energy (Note 9)
Recommended Frequency of SPI Operation
Storage Temperature
Operating Case Temperature
VESD1
VESD2
ECLAMP
fSPI
TSTG
TC
2000
200
50
3.0
- 55 to 150
- 40 to 125
V
mJ
MHz
°C
°C
Operating Junction Temperature
Power Dissipation (TA = 25° C) (Note 10)
TJ
- 40 to 150
°C
PD 2.0 W
Soldering Temperature (Note 11)
TSOLDER
260 °C
Thermal Resistance (Junction-to-Ambient)
Case 751E-04 Package
All Outputs ON (Note 12)
Single Output ON (Note 13)
RθJA
°C/W
45
60
Notes:
1. Transient capability with external 100 resistor in series with VP pin and supply.
2. Exceeding these limits may cause a malfunction or permanent damage to the device.
3. Exceeding the limits on SCLK, SI, CS, SFPD, or RST pins may cause permanent damage to the device.
4. With output OFF.
5. Continuous output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature will
require maximum output current computation using package RθJA.
6. ESD data available upon request.
7. ESD1 testing is performed in accordance with the Human Body Model (CZap = 200 pF, RZap = 1500 ).
8. ESD2 testing is performed in accordance with the Machine Model (CZap = 200pF, RZap = 0 ).
9. Maximum output clamp energy capability at 150°C junction temperature using a single non-repetitive pulse method.
10. Maximum power dissipation at indicated junction temperature with no heat sink used.
11. Lead soldering temperature limit is for 10 seconds maximum duration; not designed for immersion soldering; exceeding these limits may
cause malfunction or permanent damage to the device.Contact Motorola Sales Office for device immersion soldering time/temperature limits.
12. Thermal resistance from Junction-to-Ambient with all outputs ON and dissipating equal power.
13. Thermal resistance from Junction -to-Ambient with a single output ON.
33291
4
For More Information OMnOTTOhRiOsLAPrAoNdALuOcGt,INTEGRATED CIRCUIT DEVICE DATA
Go to: www.freescale.com

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MC33291 전자부품, 판매, 대치품
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V, -40°C TA 125°C, unless otherwise noted. Typical
values noted reflect the approximate value with VBAT = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max Unit
Digital Interface
Input Logic High Voltage (Note 22)
Input Logic Low Voltage (Note 22)
Input Logic Threshold Hysteresis (SCLK, RST, and SFPD) (Note 23)
SI Pull-Up Current (SI = 0 V)
VIH 0.7 — 1.0 VDD
VIL 0 — 0.2 VDD
VI(Hvs) 50 100 500 mV
ISI 0 10 20 µA
CS Pull-Up Current (CS = 0 V)
ICSB
0 10 20 µA
SCLK Pull-Down Current (SCLK = 5.0 V)
ISCLK 0 10 20 µA
RST Pull-Down Current (RST = 5.0 V)
SFPD Pull-Down Current (SFPD = 5.0 V)
SO High State Output Voltage (IOH = 1.0 mA)
IRST
ISFPD
VSOH
5.0 25
5.0 10
VDD -0.4 V VDD -0.2 V
50
25
µA
µA
V
SO Low State Output Voltage (IOL = -1.6 mA)
VSOL
— 0.2 0.4 V
SO Tri-State Leakage Current (CS = 0.7 VDD, 0 V < VSO < VDD)
ISOT
-10 0
10 µA
Input Capacitance (0 V < VDD < 5.5 V) (Note 24)
CIN — — 12 pF
SO Tn-State Capacitance (0 V < VDD < 5.5 V) (Note 25)
CSOT — — 20 pF
Notes:
22. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs.
23. Hysteresis is characterized, but it is not production tested.
24. Input capacitance of SI CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production
tested.
25. Tri-state capacitance of SO for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested.
RST
0.2 VDD
CS
SCLK
SI
tw(RST)
0.2 VDD
tlead
tw(SCLKH)
Don't Care
0.7 VDD
0.2 VDD
tSI(su)
0.7 VDD
Valid
0.2 VDD
tr
tw(SCLKL)
tSI(hold)
Don't Care
tlag
tf
Valid
Figure 2. Input Timing Switch Characteristics
VIH
VIL
VIH
VIL
VIH
VIL
Don't Care
VIH
VIL
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfoTArmation On This Product,
Go to: www.freescale.com
33291
7

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