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부품번호 MC33298 기능
기능 OCTAL SERIAL SWITCH (SPI Input/Output)
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MC33298 데이터시트, 핀배열, 회로
Order this document by MC33298/D
MC33298
Octal Serial Switch with
Serial Peripheral Interface I/O
The MC33298 is an eight output low side power switch with 8 bit serial input
control. The MC33298 is a versatile circuit designed for automotive
applications, but is well suited for other environments. The MC33298
incorporates SMARTMOStechnology, with CMOS logic, bipolar/MOS
analog circuitry, and DMOS power MOSFETs. The MC33298 interfaces
directly with a microcontroller to control various inductive or incandescent
loads. The circuit’s innovative monitoring and protection features are: very low
standby current, cascadable fault reporting, internal 65 V clamp on each
output, output specific diagnostics, and independent shutdown of outputs. The
MC33298 is parametrically specified over a temperature range of – 40°C TA
+125°C ambient temperature and 9.0 V VPWR 16 V supply. The
economical 20 pin DIP and SO–24 wide body surface mount plastic packages
make the MC33298 very cost effective.
Designed to Operate Over Wide Supply Voltages of 5.5 V to 26.5 V
Interfaces Directly to Microprocessor Using SPI Protocol
SPI Communication for Control and Fault Reporting
8–Bit Serial I/O is CMOS Compatible
3.0 A Peak Current Outputs with Maximum RDS(on) of 0.45 at 25°C
Outputs are Current Limited to 3.0 A to 6.0 A for Driving Incandescent
Lamp Loads
Output Voltages Clamped to 65 V During Inductive Switching
Maximum Sleep Current (IPWR) of 50 µA with VDD 2.0 V
Maximum of 4.0 mA IDD During Operation
Maximum of 2.0 mA IPWR During Operation with All Outputs “On”
Open Load Detection (Outputs “Off”)
Overvoltage Detection and Shutdown
Each Output has Independent Over Temperature Detection and Shutdown
Output Mode Programmable for Sustained Current Limit or Shutdown
Short Circuit Detect and Shutdown with Automatic Retry for Every
Write Cycle
Serial Operation Guaranteed to 2.0 MHz
SFPD
Micro–
controller
with Bus
SFPD
CSB
SCLK
SI
Reset
SO
Simplified Application
VDD VPWR
CMOS
Input
Logic
CMOS
Serial Shift
Registers
and
Latches
Updrain
DMOS
Output
Switches
and
Sense
Circuits
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
+Vbat
OCTAL SERIAL SWITCH
(SPI Input/Output)
SEMICONDUCTOR
TECHNICAL DATA
20
1
P SUFFIX
PLASTIC PACKAGE
CASE 738
DIP (16+2+2)
24
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
SOP (16+4+4)L
PIN CONNECTIONS
DIP Function SOP–24L
1 Output 7 1
2 Output 6 2
3 SCLK 3
4 SI 4
5 Ground 5
6 Ground 6
– Ground 7
– Ground 8
7 SO 9
8
CSB
10
9
Output 5
11
10 Output 4 12
11 Output 3 13
12 Output 2 14
13 SFPD 15
14 VDD 16
15 Ground 17
16 Ground 18
Ground
19
Ground
20
17 VPWR 21
18 Reset 22
19 Output 1 23
20 Output 0 24
ORDERING INFORMATION
Device
Tested Operating
Temperature Range Package
This device contains 1,200 active transistors.
Gnd
MC33298P
DIP
MC33298DW TC = – 40° to +125°C SOP–24L
MOTOROLA ANALOG IC DEVICE DATA
© Motorola, Inc. 1996
Rev 2
1




MC33298 pdf, 반도체, 판매, 대치품
MC33298
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V,
– 40°C TC 125°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ Max Unit
POWER INPUT
Supply Voltage Range
Quasi–Functional (Note 1)
Full Operational
VPWR(qf)
VPWR(fo)
5.5
9.0
V
– 9.0
– 26.5
Supply Current (all Outputs “On,” Iout = 0.5 A) (Note 2)
IPWR(on)
1.0 2.0 mA
Sleep State Supply Current (VDD = 0.5 V)
IPWR(ss)
1.0 50 µA
Sleep State Output Leakage Current (per Output, VDD = 0.5 V)
IOUT(ss)
– 50 µA
Overvoltage Shutdown
VOV
28
– 36 V
Overvoltage Shutdown Hysteresis
VOV(hys)
0.2
– 1.5 V
Logic Supply Voltage
VDD
4.5
– 5.5 V
Logic Supply Current (with any combination of Outputs “On”)
IDD –
– 4.0 mA
Logic Supply Undervoltage Lockout Threshold (Note 3)
VDD(uvlo)
2.0
– 4.5 V
POWER OUTPUT
Drain–to–Source “On” Resistance (Iout = 0.5 A, TJ = 25°C)
VPWR = 5.5 V
VPWR = 9.0 V
VPWR = 13 V
Drain–to–Source “On” Resistance (Iout = 0.5 A, TJ = 150°C)
VPWR = 5.5 V
VPWR = 9.0 V
VPWR = 13 V
RDS(on)
RDS(on)
– 1.0
0.4 0.5
0.35 0.45
– 1.8
0.75 0.9
0.65 0.8
Output Self–Limiting Current
Outputs Programmed “On”, Vout = 0.6 VDD
Output Fault Detect Threshold (Note 4)
Output Programmed “Off”
IOUT(lim)
VOUTth(F)
3.0
0.6
A
4.0 6.0
VDD
0.7 0.8
Output “Off” Open Load Detect Current (Note 5)
Output Programmed “Off,” Vout = 0.6 VDD
Output Clamp Voltage
2.0 mA Iout 200 mA
Output Leakage Current (VDD 2.0 V) (Note 6)
IOCO
VOK
IOUT(lkg)
30
50
– 50
µA
50 100
V
60 75
0 50 µA
Over Temperature Shutdown (Outputs “Off”) (Note 7)
TLIM
155
170 185 °C
Over Temperature Shutdown Hysteresis (Note 7)
TLIM(hys)
10 20 °C
NOTES: 1. SPI inputs and outputs operational; Fault reporting may not be fully operational within this voltage range.
2. Value reflects normal operation (no faults) with all outputs “on.” Each “on” output contributes approximately 20 µA to IPWR. Each output experiencing
a “soft short” condition contributes approximately 0.5 mA to IPWR. A “soft short” is defined as any load current causing the output source current to
self–limit. A “hard” output short is a very low impedance short to supply.
3. For VDD less than the Undervoltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled.
4. Output fault detect threshold with outputs programmed “off.” Output fault detect thresholds are the same for output opens and shorts.
5. Output “Off” Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open condition
when the specific output is commanded to be “off.”
6. Output leakage current measured with output “off” and at 16 V.
7. This parameter is guaranteed by design but is not production tested.
4 MOTOROLA ANALOG IC DEVICE DATA

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MC33298 전자부품, 판매, 대치품
MC33298
Figure 3. Valid Data Delay Time and
Valid Time Test Circuit
VDD = 5.0 V
Figure 4. Enable and Disable Time Test Circuit
VDD = 5.0 V
VPull–Up = 2.5 V
SCLK
MC33298
Under
Test
SO
CL = 200 pF
MC33298
CSB Under
Test
RL = 2.0 k
SO
CL = 20 pF
CL represents the total capacitance of the test fixture and probe.
CL represents the total capacitance of the test fixture and probe.
Figure 5. Vaild Data Delay Time and
Valid Time Waveforms
SCLK
trSI
0.7 VDD (2.5 V)
10 ns
50%
tfSI
10 ns
5.0 V
0.2 VDD
0
SO
(Low–to–High)
SO
(High–to–Low)
tdly(lh)
0.2 VDD
tvalid
0.7 VDD
tdly(hl)
0.7 VDD
trSO
tfSO
0.2 VDD
VOH
VOL
VOH
VOL
SO (low–to–high) is for an output with internal conditions such that
the low–to–high transition of CSB causes the SO output to switch
from high–to–low.
Figure 6. Enable and Disable Time Waveforms
trSI 10 ns
CSB 0.7 VDD
0.2 VDD (2.5 V)
90%
50%
10%
tfSI 10 ns
5.0 V
0
SO
(High–to–Low)
tSO(en)
tSO(en)
tSO(dis)
50%
tSO(dis)
VOH
VOL
SO
(Low–to–High)
VOH
50%
VOL
NOTES: 1. SO (high–to–low) waveform is for SO output with internal
conditions such that SO output is low except when an output is
disabled as a result of detecting a circuit fault with CSB in a
High Logic state (e.g., open load).
2. SO (low–to–high) waveform is for SO output with internal
conditions such that SO output is high except when an output
is disabled as a result of detecting a circuit fault with CSB in
a High Logic state (e.g., shorted load).
MOTOROLA ANALOG IC DEVICE DATA
7

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