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PDF XCR5064 Data sheet ( Hoja de datos )
| Número de pieza | XCR5064 | |
| Descripción | 64 Macrocell CPLD with Enhanced Clocking | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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APPLICATION NOTE
0
R XCR5064C: 64 Macrocell CPLD with
Enhanced Clocking
DS044 (v1.1) February 10, 2000
0 14* Product Specification
Features
• Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• High speed pin-to-pin delays of 7.5 ns
• Ultra-low static power of less than 100 µA
• 100% routable with 100% utilization while all pins and
all macrocells are fixed
• Deterministic timing model that is extremely simple to
use
• Up to 12 clocks with programmable polarity at every
macrocell
• 5V, In-System Programmable (ISP) using a JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by multiple ISP programming platforms
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG commands include: Bypass, Idcode
• Support for complex asynchronous clocking
• Innovative XPLA™ architecture combines high speed
with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard
and Xilinx CAE tools
• Reprogrammable using industry standard device
programmers
• Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
- Up to two asynchronous clocks
• Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
• Available in PLCC and VQFP packages
• Available in both Commercial and Industrial grades
Description
The XCR5064C CPLD (Complex Programmable Logic
Device) is the second in a family of CoolRunner™ CPLDs
from Xilinx Semiconductors. These devices combine high
speed and zero power in a 64 macrocell CPLD. With the
FZP design technique, the XCR5064C offers true pin-to-pin
speeds of 7.5 ns, while simultaneously delivering power
that is less than 100 µA at standby without the need for
`turbo bits' or other power down schemes. By replacing
conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs
since the bipolar era) with a cascaded chain of pure CMOS
gates, the dynamic power is also substantially lower than
any competing CPLDz. These devices are the first TotalC-
MOS PLDs, as they use both a CMOS process technology
and the patented full CMOS FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
ciently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2.0 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9.5 ns from any pin to any
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR5084C CPLDs are supported by industry stan-
dard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses Xilinx developed tools including WebFITTER.
The XCR5064C CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BPMicrosystems, SMS, and others. The XCR5064C
also includes an industry-standard, IEEE 1149.1, JTAG
interface through which In-System Programming (ISP) and
reprogramming of the device are supported.
DS044 (v1.1) February 10, 2000
www.xilinx.com
1-800-255-7778
1
1 page  
XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
R
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other architectures, the user
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR5064C device, the user knows up front that if a
given output uses five product terms or less, the
tPD = 7.5 ns, the tSU_PAL = 4 ns, and the tCO = 5.5 ns. If an
output is using six to 37 product terms, an additional 2ns
must be added to the tPD and tSU timing parameters to
account for the time to propagate through the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of our XCR5064C TotalCMOS CPL .
INPUT PIN
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
D
REGISTERED
Q tCO
OUTPUT PIN
OUTPUT PIN
GLOBAL CLOCK PIN
Figure 4: CoolRunner Timing Model
SP00441
100
TYPICAL
80
ICC
(mA)
60
40
20
0
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 5: ICC vs. Frequency at VCC = 5V, 25°C
Table 1: ICC vs. Frequency (VCC = 5.0V, 25°C)
Frequency (MHz) 0
1 20 40
Typical ICC (mA) 0.1 0.5 8.6 17.1
60
25.6
80
33.9
100
42.2
120
50.3
140
58.3
160
66.4
SP00663
180 200
74.7 82.7
5
www.xilinx.com
DS044 (v1.1) February 10, 2000
1-800-255-7778
5 Page 
XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
R
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol
Parameter
-7
Min. Max.
tPD_PAL
tPD_PLA
Propagation delay time, input (or feedback node) to output through PAL
Propagation delay time, input (or feedback node) to output through PAL
& PLA
2
3
7.5
9
tCO
tSU_PAL
tSU_PLA
tH
tCH
tCL
tR
tF
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
Clock to out (global synchronous clock from pin)
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time2
Clock High time2
Clock Low time2
Input Rise time
Input Fall time
Maximum FF toggle rate2 (1/tCH + tCL)
Maximum internal frequency2 (1/tSUPAL + tCF)
Maximum external frequency2 (1/tSUPAL + tCO)
Output buffer delay time2
Input (or feedback node) to internal feedback node delay time through
PAL
2
4.5
6
3
3
167
133
105
5
0
20
20
2.5
5
tPDF_PLA Input (or feedback node) to internal feedback node delay time through
PAL+PLA
6.5
tCF
tINIT
tER
tEA
tRP
tRR
Notes:
Clock to internal feedback node delay time
Delay from valid VCC to valid reset
Input to output disable2, 3
Input to output valid2
Input to register preset2
Input to register reset2
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
3
50
7.5
7.5
9
9
-10
Min. Max.
2 10
3 12
2 6.5
6
8
0
4
4
20
20
125
95
80
2.5
7.5
9.5
4.5
50
10
10
11
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
11
www.xilinx.com
DS044 (v1.1) February 10, 2000
1-800-255-7778
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet XCR5064.PDF ] | |
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