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PDF BUS-61553 Data sheet ( Hoja de datos )
| Número de pieza | BUS-61553 | |
| Descripción | Advanced Integrated MUX Hybrid | |
| Fabricantes | Data Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de BUS-61553 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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BUS-61553
eet4UM.cIoLm-STD-1553 ADVANMCUEXD(IANIMTE)GHRYABTREIDDUSSEERE’SALGSUOIDE
ShDESCRIPTION
taDDC’s BUS-61553 Advanced
aIntegrated Mux (AIM) Hybrid is a
.Dcomplete MIL-STD-1553 Bus
Controller (BC), Remote Terminal
wUnit (RTU), and Bus Monitor (MT)
wdevice. Packaged in a single 78-pin
wDIP package, the BUS-61553 con-
tains dual low-power transceivers,
mcomplete BC/RT/MT protocol logic, a
oMIL-STD-1553-to-host interface unit
and 8K x 16 RAM.
.cUsing an industry standard dual
transceiver and standard status and
control signals, the BUS-61553 sim-
Uplifies system integration at both the
t4MIL-STD-1553 and host processor
interface levels.
eAll 1553 operations are controlled
through the CPU access to the
shared 8K x 16 RAM. To ensure
maximum design flexibility, memory
control lines are provided for attach-
ing external RAM to the BUS-61553
address and data buses and for dis-
abling internal memory; the total
combined memory space can be
expanded to 64K x 16. All 1553 trans-
fers are entirely memory-mapped;
thus the CPU interface requires
minimal hardware and/or software
support.
The BUS-61553 operates over the
full military -55°C to +125°C temper-
ature range. Available screened to
MIL-PRF-38534, the BUS-61553 is
ideal for demanding military and
industrial microprocessor-to-1553
interface applications.
FEATURES
• Fully Intergrated Terminal
Including:
–Dual Transceiver
–BC/RT/MT Protocol
–Memory Management Unit
–Processor lnterface Logic
–8K x 16 RAM
• CMOS and Bipolar Technologies
• Internal Interrupt Status and Time
Tag Registers
• High Reliability
• 883B Processing Available
heBUS-25679
S8 1
DATA
taBUSA 4
2
3
w.DaTRANSFORMER A
TRANSCEIVER A
TX INH
TX CHANNEL A
ENCODER/
RX DECODER
RX
MEMORY
TIMING
768 µs
TIME OUT
PROTOCOL
CONTROLLER
CONTENTION
RESOLVER
CPU
TIMING
INTERRUPT
GENERATOR
CLOCK IN
MSTRCLR
SELECT
STRBD
READYD
RD/WR
MEM/REG
EXTEN
EXTLD
INT
w mBUS-25679
w .coDATA
BUS B
8
4
1
2
3
.DataSheet4UTRANSFORMER B
A15-A00
TX INH
D15-D00
TX CHANNEL B
ENCODER/
RX DECODER
RX
TRANSCEIVER B
8K x 16
SHARED RAM
RAM
PARITY
CHECKER
RT ADDR
FIGURE 1. BU-61553 BLOCK DIAGRAM
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RTAD P
RTPARERR
www© 1987, 1999 Data Device Corporation
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet BUS-61553.PDF ] | |
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