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PDF BUS-61560-xxxx Data sheet ( Hoja de datos )
| Número de pieza | BUS-61560-xxxx | |
| Descripción | MIL-STD-1553 Bc-rt-mt Integrated Terminal | |
| Fabricantes | Data Device | |
| Logotipo |  |
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BUS-61559 SERIES
MIL-STD-1553B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY’er)
DESCRIPTION
DDC’s BUS-61559 series of Advanced buffers to provide a direct interface to
Integrated Mux Hybrids with enhanced a host processor bus. Alternatively,
RT Features (AIM-HY’er) comprise a the buffers may be operated in a fully
complete interface between a micro- transparent mode in order to interface
processor and a MIL-STD-1553B to up to 64K words of external shared
Notice 2 bus, implementing Bus RAM and/or connect directly to a com-
Controller (BC), Remote Terminal (RX, ponent set supporting the 20 MHz
and Monitor Terminal (MT) modes. STANAG-3910 bus.
Packaged in a single 78-pin DIP or
82-pin flat package the BUS-61559 The memory management scheme
series contains dual low-power trans- for RT mode prevails an option for
ceivers and encoder/decoders, com- separation of broadcast data, in com-
plete BC/RT/MT protocol logic, memory pliance with 1553B Notice 2. A circu-
management and interrupt logic, 8K x 16 lar buffer option for RT message data
of shared static RAM, and a direct, blocks offloads the host processor for
buffered interface to a host processor bus. bulk data transfer applications.
The BUS-61559 includes a number of
advanced features in support of
MIL-STD-1553B Notice 2 and STANAG
Another feature besides those listed
to the right, is a transmitter inhibit con-
trol for the individual bus channels.
3838. Other salient features of the The BUS-61559 series hybrids oper-
BUS-61559 serve to provide the bene- ate over the full military temperature
fits of reduced board space require- range of -55 to +125”C and MIL-PRF-
ments enhanced software flexibility, 38534 processing is available. The
and reduced host processor overhead hybrids are ideal for demanding mili-
The BUS-61559 contains internal
address latches and bidirectional data
tary and industrial microprocessor-to-
1553 applications
FEATURES
• Complete Integrated 1553B
Notice 2 Interface Terminal
• Functlonal Superset of BUS-
61553 AlM-HYSeries
• Internal Address and Data
Buffers for Dlrect Interface to
Processor Bus
• RT Subaddress Circular Buffers
to Support Bulk Data Transfers
• Optlonal Separatlon of
RT Broadcast Data
• Internal Interrupt Status and
Time Tag Registers
• Internal ST Command
Illegalization
• MIL-PRF-38534 Processing
Available
(ILLEGALIZATION ILLENA
ENABLE)
ILLEGALLIZATION
LOGIC
BUS-25679
81
7
5
2
43
LOW-POWER
TRANSCEIVER
A
8K x 16
DUAL
PORT
RAM
CLK IN (16MHz)
TX_INH_A
BUS-25679
81
7
5
2
43
LOW-POWER
TRANSCEIVER
A
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
TX_INH_A
(RT ADDRESS)
RTAD 4-∅, RTADP
(BROADCAST
ENABLE)
(RTFAIL,
RTFLAG)
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
BRO_ENA
RTFAIL
RTFLAG
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
MEMORY DATA
DATA
BUFFERS*
D15-D∅
(PROCESSOR
DATA)
MEMORY ADDRESS
ADDRESS
LATCHES/
BUFFERS*
A15-A∅
(PROCESSOR
ADDRESS)
ADDR_LAT (ADDRESS
LATCH
CONTROL)
MEMORY
MANAGEMENT,
SHARED
RAM/
PROCESSOR
INTERFACE,
INTERRUPT
LOGIC
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
IOEN, READYD
(PROCESSOR
CONTROL)
INT
MEMEN-OUT,MEMWR, MEMOE
MEMENA-IN
(INTERRUPT
REQUEST)
(MEMORY
CONTROL)
SSFLAG
TAGCLK
(SUBSYSTEM
FLAG)
(TIME TAG
CLOCK)
BU-61559 BLOCK DIAGRAM
© 1990, 1999 Data Device Corporation
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