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D6571E PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 D6571E
기능 Chip for an All-Digital Telephone Answering Machine with Flash Memory Interface
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D6571E 데이터시트, 핀배열, 회로
D6571E Data Sheet
A
D6571E
EASYTADChip for an All-Digital
Telephone Answering Machine
with Flash Memory Interface
DS6571E.2
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986-4300 FAX: 408 986-4490
1




D6571E pdf, 반도체, 판매, 대치품
D6571E Data Sheet
5 V OPERATION.............................................................................................................................................................................. 106
3.3 V OPERATION........................................................................................................................................................................... 107
DETECTORS CHARACTERISTICS .............................................................................................................................................. 109
DTMF & VOX CHARACTERISTICS........................................................................................................................................... 109
Call Progress Tone Detector Performance................................................................................................................................... 109
Caller ID FSK Demodulator Performance ..................................................................................................................................... 109
Caller Alert Signal / Idle State Tone Alert Signal........................................................................................................................ 110
DS6571E.2
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986-4300 FAX: 408 986-4490
4

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D6571E 전자부품, 판매, 대치품
D6571E Data Sheet
PIN DESCRIPTIONS
D6571E-11 (DSP)
PIN
Name
HSTDB0 (LSB)
No.
14
HSTDB1
HSTDB2
HSTDB3
HSTDB4
HSTDB5
HSTDB6
HSTDB7 (MSB)
HI/ LO
HSTRD
HSTWR
ACK
DSPCS
ADDRO (LSB)
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15 / CE3
CE1
CE 0
CE2/VPCS
ALE/DI
CLE/DO
MDB0 (LSB)
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
13
12
11
10
9
8
7
4
5
6
3
77
59
60
61
62
63
64
65
66
67
68
69
70
71
72
2
1
80
75
76
78
79
39
40
41
42
43
44
45
46
47
48
49
50
51
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
I
I
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
O
O
O
O
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Description
HOST DATA BUS. The HOST writes commands and reads status to/from the D6571E via this
bus. The HI/ LO pin selects between the low byte and the high byte of the command/status.
This bus is used for input when HSTWR is low, and for output when HSTRD is low.
It has high impedance when HSTWR and HSTRD are high or RESET is high.
Active only during Host Read.
HIGH/LOW BYTE SELECT. When this signal is low, the HOST can read/write the low byte
of the status/command. When high , the high byte is selected.
HOST READ. When low, the HOST reads the low/high byte of the status word.
HOST WRITE. When low the HOST writes commands to the D6571E via HSTDB 0-7.
HOST ACKNOWLEDGE. This pin goes low when the D6571E send a status word to the
HOST. It goes high when the HOST reads the high byte of the status word.
DSP Chip Select (Optional connection to ground recommended, if not used.)
EXTERNAL MEMORY ADDRESS BUS
Chip Enable 3 for flash device or Address 15 for external 64K/ EPROM
Chip Enable 1 for flash device
Chip Enable 0 for flash device
Chip Enable 2 for flash device or Voice Prompt ROM/EPROM Chip Enable
Address Latch Enable for Samsung flash devices; Data Input for Toshiba device
Command Latch Enable for Samsung flash devices; Data Output for Toshiba device
EXTERNAL MEMORY DATA BUS.
DS6571E.2
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986-4300 FAX: 408 986-4490
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전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



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부품번호상세설명 및 기능제조사
D6571E

Chip for an All-Digital Telephone Answering Machine with Flash Memory Interface

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