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PDF MTV312MV64 Data sheet ( Hoja de datos )
| Número de pieza | MTV312MV64 | |
| Descripción | 8051 Embedded Monitor Controller | |
| Fabricantes | Myson Technology | |
| Logotipo |  |
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om MTV312M64
8051 Emebeetd4dUe.cd Monitor Controller Flash Type with ISPGENERAL DESCRIPTIONS
hThe MTV312M micro-controller is an 8051 CPU core
taSembedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core,
a1024-byte SRAM, 14 built-in PWM DACs, VESA
.DDDC interface, 4-channel A/D converter, and a 64K-
wwwbyte internal program Flash-ROM.
FEATURES
• 8051 core, 12MHz operating frequency with double
CPU clock option
• 0.35um process; 5V/3.3V power supply and I/O;
3.3V core operating
• 1024-byte RAM; 64K-byte program Flash-ROM
support In System Programming (ISP)
• Maximum 14 channels of PWM DAC
• Maximum 31 I/O pins
• SYNC processor for composite
separation/insertion, H/V polarity/frequency check
and polarity adjustment
m• Built-in low power reset circuit
• Built-in self-test pattern generator with four free-
orunning timings
• Compliant with VESA DDC1/2B/2Bi/2B+ standard
.c• Dual slave IIC addresses; H/W auto transfer
DDC1/DDC2x data
• Single master IIC interface for internal device
Ucommunication
• Maximum 4-channel 6-bit ADC
t4• Watchdog timer with programmable interval
• Flash-ROM program code protection selection
e• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package
heBLOCK DIAGRAM
taSP1.0-7
aP3.0-2
P3.4-5
.D8051
CORE
P0.0-7
P2.0-3
RD
WR
ALE
INT1
wRST
X1
wwX2
P0.0-7
P2.0-3
RD
WR
ALE
INT1
XFR
AD0-3 ADC
AUXRAM &
DDCRAM
H/VSYNC
CONTROL
HSYNC
VSYNC
HBLANK
VBLANK
mP6.0-7
.coP5.0-6
UP4.0-2
AUX
I/O
PWM DAC
DA0-13
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
ataSheet4Myson Century, Inc.
Taiwan:
USA:
.DNo. 2, Industry East Rd. III,
4020 Moorpark Avenue Suite 115
wScience-Based Industrial Park, Hsin-Chu, Taiwan San Jose, CA, 95117
wwTel: 886-3-5784866 Fax: 886-3-5784349
Tel: 408-243-8388 Fax: 408-243-3188
www.myson.com.tw
Rev. 1.2 March 2003
page 1 of 34
1 page  
HBLANK/P4.1
STOUT/P4.2
HSYNC
VSYNC
MTV312M64
33 35 37 O Horizontal blank (CMOS) / General purpose Output (CMOS)
11 14 15 O Self-test video output (CMOS) / General purpose Output (CMOS)
39 41 43 I Horizontal SYNC or Composite SYNC Input
40 42 44 I Vertical SYNC input
Page 5 of 34
5 Page 
MTV312M64
DA7
DA8
DA9
DA10
DA11
DA12
DA13
F27h(r/w)
F28h(r/w)
F29h(r/w)
F2Ah(r/w)
F2Bh(r/w)
F2Ch(r/w)
F2Dh(r/w)
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8
Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13
DA0-13 (r/w) : The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.
H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion. SYNC inputs
presence check, frequency counting, polarity detection and control, as well as the protection of VBLANK output
while VSYNC speeds up in high DDC communication clock rate.
Based on the digital filter, the HSYNC present and frequency function block treat any pulse longer than the
specified time period as pulse, and the specified time period is controlled by (DF1,DF0) bits. The VSYNC digital
filter has no control bit. It works as (DF1,DF0) = (0, 0) of HSYNC.
VSYNC
HSYNC
Digital Filter
Present
Check
Vpre
Polarity Check &
Freq. Count
Vfreq
Vpol
Vbpl
CVSYNC
XOR
Vself
Present
Check
CVpre
XOR VBLANK
Digital Filter
Polarity Check &
Sync Seperator
Hpol
Present Check &
Freq. Count
Hpre
Hfreq
Composite
Pulse Insert
XOR
Hself
H/V SYNC Processor Block Diagram
Hbpl
XOR
HBLANK
Page 11 of 34
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet MTV312MV64.PDF ] | |
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