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PDF IT8152F Data sheet ( Hoja de datos )

Número de pieza IT8152F
Descripción (IT8152F/G) Risc to Pci Companion Chip For SA-1110
Fabricantes Integrated Technology Express　
Logotipo Integrated Technology Express Logotipo



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No Preview Available ! IT8152F Hoja de datos, Descripción, Manual

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.comIT8152F / IT8152G
UAdvanced RISC-to-PCI Companion Chip
www.DataSheet4Preliminary Specification V0.3.4
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IT8152F pdf
IT8152F/IT8152G
8.4.2.1 PCI Interrupt Acknowledge Cycle (PIAC) Address 0x43F00808 ....................... 41
8.4.2.2 PCI Special Cycle (PSC) Address 0x43F0080C................................................. 42
8.4.3 CPU/PCI Bridge Configuration Registers (Function 0) ....................................................... 42
8.4.3.1
8.4.3.2
8.4.3.3
8.4.3.4
8.4.3.5
8.4.3.6
8.4.3.7
8.4.3.8
8.4.3.9
8.4.3.10
8.4.3.11
8.4.3.12
8.4.3.13
8.4.3.14
8.4.3.15
Vendor Identification Register (VID) Offset 0x00-01........................................... 42
Device Identification Register (DID) Offset 0x02-0x03 ....................................... 42
PCI Command Register (PCICMD) Offset 0x04-0x05........................................ 43
PCI Status Register (PCISTS) Offset 0x06-0x07................................................ 44
Revision ID Register (RID) Offset 0x08 ............................................................... 44
Class Code Register (CLASSC) Offset 0x09-0x0B ............................................ 44
Header Type Register (HEADT) Offset 0x0E...................................................... 45
PCI Memory Base Address Register (PMBAR) Offset 0x10.............................. 45
PCI I/O Base Address Register (PIOBAR) Offset 0x14...................................... 45
PCI Memory Address Prefix Register for Bank 4 (PMAPR4) Offset 0x40 ........ 45
PCI Memory Address Prefix Register for Bank 5 (PMAPR5) Offset 0x44 ........ 45
PCI I/O Address Prefix Register (PIOAPR) Offset 0x48..................................... 46
Prefetch Control Register (PCR) Offset 0x4C..................................................... 46
Partial Read Base Address Register n (PRBARn) .................................................. 46
Partial Read Control Register n (PRCRn) ................................................................ 47
9. PCI-to-LPC Bridge ............................................................................................................................................. 49
9.1 Overview.............................................................................................................................................. 49
9.2 Features............................................................................................................................................... 49
9.3 Configuration Register Description .................................................................................................... 50
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.3.11
9.3.12
9.3.13
Vendor Identification Register (VID) Offset 0x00-0x01 .................................................. 50
Device Identification Register (DID) Offset 0x02-0x03................................................... 50
PCI Command Register (PCICMD) Offset 0x04-0x05 ................................................... 51
PCI Status Register (PCISTS) Offset 0x06-0x07 ........................................................... 52
Revision ID Register (RID) Offset 0x08 .......................................................................... 52
Class Code Register (CLASSC) Offset 0x09-0x0B........................................................ 52
Header Type Register (HEADT) Offset 0x0E ................................................................. 53
Base Address Register (BAR) Offset 0x10 ..................................................................... 53
Serial IRQ Control Register (SERIRQC) Offset 0x49 .................................................... 53
Bridge Control Register (BCR) Offset 0x4C.................................................................... 54
Bridge Status Register (BSR) Offset 0x4D ..................................................................... 55
Discard Timer Register (DTR) Offset 0x4F..................................................................... 55
LPC I/O Space Base Address Register (LISBAR) Offset 0x50 ..................................... 55
10.Chaining DMA Controller................................................................................................................................... 57
10.1 Overview.............................................................................................................................................. 57
10.2 Features............................................................................................................................................... 57
10.3 Block Diagram ..................................................................................................................................... 57
10.4 DMA Operation.................................................................................................................................... 58
10.4.1 Non-Chaining Mode DMA ..................................................................................................... 58
10.4.2 Chaining Mode DMA ............................................................................................................. 59
10.5 Register Description............................................................................................................................ 60
10.5.1 CDMA Configuration Registers (Function 1) ....................................................................... 62
10.5.1.1
10.5.1.2
10.5.1.3
10.5.1.4
10.5.1.5
Vendor Identification Register (VID) VID, Offset 0x00-0x11 .............................. 62
Device Identification Register (DID) DID, Offset 0x02-0x03 .............................. 62
PCI Command Register (PCICMD) PCICMD, Offset 0x04-0x05....................... 62
PCI Status Register (PCISTS) PCISTS, Offset 0x06-0x07................................ 63
Revision ID Register (RID) RID, Offset 0x08 ...................................................... 63
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ii IT8152F/IT8152G V0.3.4

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IT8152F arduino
IT8152F/IT8152G
16.4 Register Descriptions........................................................................................................................184
16.4.1 Port Data Registers (GPDR) GPDR Offset 0x00..........................................................184
16.4.2 General Control Register (GCR) GCR Offset 0x02......................................................184
16.4.3 Port Control n Registers (GPCnR) .....................................................................................185
16.4.4 Port Interrupt Control Registers (GPICR) GPICR Offset 0x0C ...................................186
16.4.5 Port Interrupt Status Registers (GPISR) GPISR Offset 0x0E......................................188
17.DC Characteristics ...........................................................................................................................................189
18.AC Characteristics ...........................................................................................................................................191
19.Package Information ........................................................................................................................................197
19.1 QFP 208L Outline Dimensions ........................................................................................................197
19.2 LBGA 208L Outline Dimensions ......................................................................................................198
20.Ordering Information ........................................................................................................................................199
Timing Diagrams
Figure 18-1. CPU Read Cycle: Read Data Timing..............................................................................................191
Figure 18-2. CPU Write Cycle: Write Data Timing ..............................................................................................191
Figure 18-3. SMC Address, Control and Read Data Timing ..............................................................................192
Figure 18-4. SMC DQM, Write Data Timing ........................................................................................................193
Figure 18-5. Cold Reset Timing............................................................................................................................194
Figure 18-6. Warm Reset Timing..........................................................................................................................194
Figure 18-7. AC9’ 7 Sync and Data Timing ..........................................................................................................195
Figure 18-8. UART Rx Timing...............................................................................................................................196
Figure 18-9. GPIO Interrupt Timing (Falling Edge Trigger) ................................................................................196
Figure 18-10. GPIO Interrupt Timing (Rising Edge Trigger)...............................................................................196
Figures
Figure 6-1. IT8152 Clock Tree Block Diagram ...................................................................................................... 23
Figure 7-1. Memory Controller Block Diagram ...................................................................................................... 31
Figure 8-1. CPU to PCI Bridge Block Diagram...................................................................................................... 37
Figure 10-1. CDMA System Architecture............................................................................................................... 57
Figure 12-1. USB States ......................................................................................................................................... 84
Figure 12-2. List Priority within a USB Frame........................................................................................................ 86
Figure 12-3. Control Bulk Service Ratio of 4:1 ...................................................................................................... 87
Figure 12-4. List Service Flow ................................................................................................................................ 89
Figure 12-5. Endpoint Descriptor Service Flow ..................................................................................................... 91
Figure 12-6. Endpoint Descriptor............................................................................................................................ 93
Figure 12-7. Transfer Descriptor Service Flow...................................................................................................... 94
Figure 12-8. Standard Token Packet Format ......................................................................................................116
Figure 12-9. SOF Token Packet Format..............................................................................................................116
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viii IT8152F/IT8152G V0.3.4

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