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PDF NB6L239 Data sheet ( Hoja de datos )
| Número de pieza | NB6L239 | |
| Descripción | 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider | |
| Fabricantes | ON Semiconductor | |
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NB6L239
2.5V / 3.3V Any Differential
Clock IN to Differential
LVPECL OUT ÷1/2/4/8,
÷2/4/8/16 Clock Divider
Description
The NB6L239 is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive a pair of differential
LVPECL outputs. (More device information on page 7). The
NB6L239 is a member of the ECLinPS MAX™ Family of the high
performance clock products.
Features
• Maximum Clock Input Frequency, 3.0 GHz
• CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL
• EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS
• Rise/Fall Time 65 ps Typical
• < 10 ps Typical Output−to−Output Skew
• Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
• Internal 50 W Termination Provided
• Random Clock Jitter < 1 ps RMS
• QA B1 Edge Aligned to QBBn Edge
• Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
• Master Reset for Synchronization of Multiple Chips
• VBBAC Reference Output
• Synchronous Output Enable/Disable
• These Devices are Pb−Free and are RoHS Compliant
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1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB6L
239
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
SELA0
SELA1
CLK
VT 50 W
50 W
CLK
B1
A
B2
B4
B8
QA
QA
VBBAC
EN
SELB0
SELB1
MR
+
B2
B B4
B8
B16
Figure 1. Simplified Logic Diagram
QB
QB
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 6
1
Publication Order Number:
NB6L239/D
1 page  
NB6L239
Table 6. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(VCC = 2.375 V to 3.465 V, VEE = 0 V)
−405C
255C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE Power Supply Cur-
30
40
50
30
40
50
30
40
50 mA
rent
VOH
Output HIGH
Voltage (Notes 2, 3)
VCC = 3.3 V
VCC = 2.5 V
VCC−1150
2150
1350
VCC−1060
2240
1440
VCC−950
2350
1550
VCC−1100
2200
1400
VCC−1015
2285
1485
VCC − 900
2400
1600
VCC−1050
2250
1450
VCC −980
2320
1520
VCC − 850
2450
1650
mV
VOL Output LOW Voltage VCC−1935 VCC−1775 VCC−1630 VCC−1875 VCC−1735 VCC−1580 VCC−1810 VCC−1675 VCC−1530 mV
(Notes 2, 3)
VCC = 3.3 V
VCC = 2.5 V
1365
565
1525
725
1670
870
1430
630
1565
765
1720
920
1490
690
1625
825
1770
970
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 7, 10)
Vth
Input Threshold Ref-
100
erence Voltage
(Note 4)
VCC − 100
100
VCC − 100
100
VCC − 100 mV
VIH Single−ended Input Vth + 100
HIGH Voltage
VCC
Vth + 100
VCC
Vth + 100
VCC
mV
VIL
Single−ended Input
VEE
LOW Voltage
Vth − 100
VEE
Vth − 100
VEE
Vth − 100 mV
VBBAC
Output Voltage Ref-
erence @ 100 mA
(Note 7)
VCC = 3.3 V
VCC = 2.5 V
VCC−1460
1840
1040
VCC−1330
1970
1170
VCC−1200
2100
1300
VCC−1460
1840
1040
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 6)
VCC−1340
1960
1160
VCC−1200
2100
1300
VCC−1460
1840
1040
VCC−1350
1950
1150
VCC−1200
2100
1300
mV
VIHD
Differential Input
HIGH Voltage
100
VCC 100
VCC
100
VCC
mV
VILD
Differential Input
LOW Voltage
VEE
VCC – 100
VEE
VCC – 100
VEE
VCC – 100 mV
VCMR
Input Common
Mode Range (Differ-
ential Cross−point
Voltage) (Note 5)
50
VCC – 50
50
VCC – 50
50
VCC – 50 mV
VID Differential Input
100
Voltage (VIHD(CLK) −
VILD(CLK)) and
(VIHD(CLK)−VILD(CLK))
VCC −
VEE
100
VCC −
VEE
100
VCC −
VEE
mV
RTIN
Internal Input Ter-
45
50
55
45
50
55
45
50
55 W
mination Resistor
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC.
3. Outputs loaded with 50 W to VCC – 2.0 V for proper operation.
4. Vth is applied to the complementary input when operating in single−ended mode.
5. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC.
6. Input and output voltage swing is a single−ended measurement operating in differential mode.
7. VBBAC used to rebias capacitor−coupled inputs only (see Figures 16 and 17).
http://onsemi.com
5
5 Page 
NB6L239
ORDERING INFORMATION
Device
Package
Shipping†
NB6L239MNG
QFN−16, 3 x 3 mm
(Pb−Free)
123 Units / Rail
NB6L239MNR2G
QFN−16, 3 x 3 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPS I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NB6L239.PDF ] | |
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