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PDF N87C251SB Data sheet ( Hoja de datos )
| Número de pieza | N87C251SB | |
| Descripción | (N87C251SA/SB/SP/SQ) High Performance CHMOS Microcontroller | |
| Fabricantes | Intel | |
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CHMH8OUIXGS.CHcM2o-5PImC1ESRRAOF/OCSOBR/MNSTAPRN/SOCQLELERCommercial/Express
eet4J Real Time and Programmed Wait State
hBus Operation
SJ Binary-code Compatible with MCS® 51
ta mJ Pin Compatible with 44-lead PLCC and
.Da o40-lead PDIP MCS 51 Sockets
J Register-based MCS® 251 Architecture
w .c— 40-byte Register File
— Registers Accessible as Bytes, Words,
w and Double Words
w UJ Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
t4Instructions
— Compare and Conditional Jump
Instructions
e— Expanded Set of Move Instructions
eJ Linear Addressing
J 256-Kbyte Expanded External Code/Data
hMemory Space
J ROM/OTPROM/EPROM Options:
S16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
taJ 16-bit Internal Code Fetch
J 64-Kbyte Extended Stack Space
aJ On-chip Data RAM Options:
m1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
.D oJ 8-bit, “Min” 2-clock External Code Fetch
.cin
UPage Mode
J User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
J 32 Programmable I/O Lines
J Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
J Three Flexible 16-bit Timer/counters
J Hardware Watchdog Timer
J Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
J Programmable Serial I/O Port
— Framing Error Detection
— Automatic Address Recognition
J High-performance CHMOS Technology
J Static Standby to 16-MHz Operation
J Complete System Development
Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
J Package Options (PDIP, PLCC, and
Ceramic DIP)
J Fast MCS 251 Instruction Pipeline
w et4This document contains information on products with “[M] [C] '94 '95 C” as the last line of the top marking
diagram. A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-
w ecode compatible with MCS 51 microcontrollers and pin compatible with 40-lead PDIP and 44-lead PLCC
hMCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing,
w Sand efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
taavailable with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without
ROM/OTPROM/EPROM. A variety of features can be selected by new user-programmable configurations.
w.DaInformation in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of
wany patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
wIntel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor varia-
tions to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2004
July 2004
Order Number: 272783-004
1 page  
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8XC251SA/SB/SP/SQ Memory Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory (FF:FFF8H–FF:FFFFH are internally decoded for Configuration
Byte data in all ROM/OTPROM/EPROM devices with EA# = 1. For all devices
with EA# = 0, the last 8 bytes of the external address range FF:XFF8H–
FF:XFFFH contain Configuration Byte information).
1, 3, 10
FF:3FFFH
FF:0000H
External memory or for internal ROM/OTPROM/EPROM devices: 16-Kbytes of
internal addresses as determined by the EA# pin (Table 8). Note: 8-Kbyte internal 3, 4, 5
ROM/OTPROM/EPROM array addresses end at FF:1FFFH.
FE:FFFFH
FE:0000H
External Memory
3
FD:FFFFH
FD:0000H
Reserved
6
FC:FFFFH
FC:0000H
Reserved
6
FB:FFFFH
04:0000H
Reserved
6
03:FFFFH
03:0000H
Reserved
6
02:FFFFH
02:0000H
Reserved
6
01:FFFFH
01:0000H
External Memory
3
00:FFFFH
00:E000H
External memory or with EMAP# bit = 0 this address range for 16-Kbyte devices
is redirected to internal ROM/OTPROM/EPROM array region.
5, 7
00:DFFFH
00:0420H
External Memory
7
00:041FH
00:0080H
On-chip RAM (512 byte RAM devices end at 00:021FH
7
00:007FH
00:0020H
On-chip RAM
8
00:001FH
00:0000H
Storage for R0–R7 of Register File
2, 9
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. The special function registers (SFRs) and the register file have separate internal address spaces.
3. Data in this area is accessible by indirect addressing only.
4. Devices can reset into different internal or external starting locations depending on the state of EA#
and configuration register information (see EA#. See also UCONFIG1:0 bit definitions).
5. The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map
into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal
ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte
ROM/OTPROM/EPROM devices.
6. This reserved area returns unspecified values and writes no data.
7. Data is accessible by direct and indirect addressing.
8. Data is accessible by direct, indirect, and bit addressing.
9. Data is accessible by direct, indirect, and register addressing.
10. Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
5
5 Page 
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate
Function
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
I/O Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
PSEN#
O Program Store Enable. Read signal output. This output is asserted
for a memory address range that depends on bits RD0 and RD1 in
configuration byte UCONFIG0 (see RD# and Table 9):
—
RD#
O Read or 17th Address Bit (A16). Read signal output to external data P3.7/A16
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and
):
RST
I Reset. Reset input to the chip. Holding this pin high for 64 oscillator —
periods while the oscillator is running resets the device. The port pins
are driven to their reset
applied, whether or not
tchoenodsitcioilnlastowrhisenruannvoinltga.gTehgisrepaintehr athsaannVinIHte1ri-s
nal pulldown resistor, which allows the device to be reset by connect-
ing a capacitor between this pin and VCC.
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
RXD
I/O Receive Serial Data. RXD sends and receives data in serial I/O mode P3.0
0 and receives data in serial I/O modes 1, 2, and 3.
T1:0
I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
P3.5:4
T2 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal P1.0
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
T2EX
I Timer 2 External Input. In timer 2 capture mode, a falling edge ini- P1.1
tiates a capture of the timer 2 registers. In auto-reload mode, a falling
edge causes the timer 2 registers to be reloaded. In the up-down
counter mode, this signal determines count direction: 1=up, 0=down.
TXD
O Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 P3.1
and transmits serial data in serial I/O modes 1, 2, and 3.
VCC
VCC2
PWR
PWR
Supply Voltage. Connect this pin to the +5V supply voltage.
Secondary Supply Voltage 2. This supply voltage connection is pro-
vided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB
as a pin-for-pin replacement for the
nected without loss of compatibility.
8(NXoCt5a1vFaXila, bVlSeSo2 ncaDnIPb)e
uncon-
—
—
VPP
I Programming Supply Voltage. The programming supply voltage is EA#
applied to this pin for programming the on-chip OTPROM/EPROM.
VSS GND Circuit Ground. Connect this pin to ground.
—
† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
11
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