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PDF ST92R195B Data sheet ( Hoja de datos )
| Número de pieza | ST92R195B | |
| Descripción | ROMLESS HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST92R195B
ROMLESS HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s 0°C to +70°C Operating Temperature Range
available
s Up to 24 MHz Operation @ 5V±10%
s Minimum instruction cycle time: 375ns at
16 MHz internal clock
s 4 Mbytes address space
s 256 Bytes RAM of Register file (accumulators or
index registers)
s 1024 Bytes of on-chip static RAM
s 8K Bytes of TDSRAM (Teletext and Display
Storage RAM)
s 80-lead QFP package
s 23 fully programmable I/O pins
s Serial Peripheral Interface
s Flexible Clock controller for OSD, Data Slicer
and Core clocks running from one single low
frequency external crystal.
s Enhanced Display Controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot Matrix, 512 ROM characters, defin-
able by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
s Teletext unit, including Data slicer, Acquisition
Unit and 8 Kbytes TDSRAM for Data Storage
s VPS and Wide Screen Signalling slicer
s Integrated Sync Extractor and Sync Controller
s 14-bit Voltage Synthesis for tuning reference
voltage
s Up to 8 External Interrupts plus 1 non-maskable
interrupt
QFP80
s 8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
s 16-bit Watchdog timer with 8-bit prescaler
s One 16-bit standard timer with 8-bit prescaler
s 4-channel Analog-to-Digital converter; 5-bit
guaranteed
s Rich instruction set and 14-Addressing modes
Versatile Development Tools, including Assem-
bler, Linker, C-compiler, Archiver, Source Level
Debugger and Hardware Emulators with Real-
Time Operating System available from third par-
ties
Device Summary
Device
ST92R195B9
Program
Memory
ROMLESS
TDS
RAM
VPS/
WSS
Package
8K Yes PQFP80
January 2000
Rev. 2.2
1/18
1
1 page  
ST92R195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
ADDR[15:0] External memory interface address
bus.
CVBS1 Composite video input signal for the Tele-
text slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
CVBSO, JTDO, JTCK Test pins: leave floating.
DAT[7:0] External memory interface data bus.
DSN Data strobe for external memory interface.
FB Fast Blanking. Video analog DAC output.
GND Digital circuit ground.
GNDA Analog circuit ground (must be tied exter-
nally to digital GND).
GNDM External memory interface ground.
HSYNC/CSYNC Horizontal/Composite sync. Hori-
zontal or composite video synchronisation input to
OSD. Positive or negative polarity.
JTRST0 Test pin: must be tied to GND.
MCFM Analog pin for the display pixel frequency
multiplier.
MMU[5:0] External memory interface MMU seg-
ment bus
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
RESET Reset (input, active low). The ST9+ is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
RWN Read/Write strobe for external memory in-
terface.
TEST0 Test pin: must be tied to VDDA.
TXCF Analog pin for the teletext PLL.
VDD Main power supply voltage (5V ±10%, digital)
VDDA Analog power supply (must be tied external-
ly to VDDA).
VDDM External memory interface power supply.
VSYNC Vertical Sync. Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
WSCF, WSCR Analog pins for the VPS/WPP slic-
er. These pins must be tied to ground or not con-
nected.
P0[2:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]- I/O
Port Lines (Input/Output, TTL or CMOS compati-
ble). 23 lines grouped into I/O ports, bit program-
mable as general purpose I/O or as Alternate func-
tions (see I/O section).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
Each pin of the I/O ports of the ST92R195B may
assume software programmable Alternate Func-
tions as shown in the Pin Configuration drawings.
Table 1. shows the Functions allocated to each I/O
Port pin.
5/18
5 Page 
ST92R195B - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VSSA
VDDA
VI
Parameter
Supply Voltage
Analog Ground
Analog Supply Voltage
Input Voltage
VAI Analog Input Voltage (A/D Converter)
VO
TSTG
IINJ
Output Voltage
Storage Temperature
Pin Injected Current
Maximum Accumulated Pin
Injected Current In Device
Value
VSS - 0.3 to VSS + 7.0
VSS - 0.3 to VSS + 0.3
VDD -0.3 to VDD +0.3
VSS - 0.3 to VDD +0.3
VSS - 0.3 to VDD +0.3
VSSA - 0.3 to VDDA +0.3
VSS - 0.3 to VDD + 0.3
- 55 to + 150
- 5 to + 5
- 50 to +5 0
Unit
V
V
V
V
V
V
°C
mA
mA
Note: Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
TA
VDD
VDDA
fOSCE
fOSCI
Parameter
Operating Temperature
Supply Voltage
Analog Supply Voltage (PLL)
External Oscillator Frequency
Internal Clock Frequency (INTCLK)
Value
Min.
Max.
0 70
4.5 5.5
4.5 5.5
3.3 8.7
24
Unit
°C
V
V
MHz
MHz
11/18
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