PDF MT4C4M4E9 Data sheet ( Hoja de datos )

Número de pieza	MT4C4M4E9
Descripción	4 MEG x 4 EDO DRAM
Fabricantes	Micron Technology
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DRAM 4 MEG x 4 EDO DRAM MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9 FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or +5V ±10%) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, HIDDEN and CAS#- BEFORE-RAS# (CBR) • Optional Self Refresh (S) for low-power data retention • 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) • Extended Data-Out (EDO) PAGE MODE access cycle • 5V-tolerant inputs and I/Os on 3.3V devices OPTIONS MARKING • Voltages 3.3V 5V LC C • Refresh Addressing 2,048 (i.e. 2K) Rows 4,096 (i.e. 4K) Rows E8 E9 • Packages Plastic SOJ (300 mil) Plastic TSOP (300 mil) DJ TG • Timing 50ns access 60ns access -5 -6 • Refresh Rates Standard Refresh Self Refresh (128ms period) None S • Part Number Example: MT4LC4M4E8DJ-6 Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in two places - MT4LC4M4E8. The third field distinguishes the low voltage offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field distinguishes various options: E8 designates a 2K refresh and E9 designates a 4K refresh for EDO DRAMs. KEY TIMING PARAMETERS SPEED -5 -6 tRC 84ns 104ns tRAC 50ns 60ns tPC 20ns 25ns tAA 25ns 30ns tCAC 13ns 15ns tCAS 8ns 10ns PIN ASSIGNMENT (Top View) 24/26-Pin SOJ (DA-2) 24/26-Pin TSOP (DB-2) VCC DQ1 DQ2 WE# RAS# NC/A11 1 2 3 4 5 6 A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 VSS VCC 1 25 DQ4 DQ1 2 24 DQ3 DQ2 3 23 22 CAS# WE# OE# RAS# NC/A11 4 5 6 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 VSS 25 DQ4 24 DQ3 23 CAS# 22 OE# 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS * NC on 2K refresh and A11 on 4K refresh options. Note: The “#” symbol indicates signal is active LOW. 4 MEG x 4 EDO DRAM PART NUMBERS PART NUMBER MT4LC4M4E8DJ MT4LC4M4E8DJS MT4LC4M4E8TG MT4LC4M4E8TGS MT4LC4M4E9DJ MT4LC4M4E9DJS MT4LC4M4E9TG MT4LC4M4E9TGS MT4C4M4E8DJ MT4C4M4E8DJS MT4C4M4E8TG MT4C4M4E8TGS MT4C4M4E9DJ MT4C4M4E9DJS MT4C4M4E9TG MT4C4M4E9TGS Vcc 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 5V 5V 5V 5V REFRESH 2K 2K 2K 2K 4K 4K 4K 4K 2K 2K 2K 2K 4K 4K 4K 4K PACKAGE SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP REFRESH Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 con- figuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address 4 Meg x 4 EDO DRAM D47.pm5 – Rev. 3/97 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1997, Micron Technology, Inc. 1 page TECHNOLOGY, INC. 4 MEG x 4 EDO DRAM TRUTH TABLE FUNCTION Standby READ EARLY WRITE READ WRITE EDO-PAGE-MODE 1st Cycle READ 2nd Cycle EDO-PAGE-MODE 1st Cycle EARLY WRITE 2nd Cycle Any Cycle EDO-PAGE-MODE 1st Cycle READ-WRITE 2nd Cycle HIDDEN READ REFRESH WRITE RAS#-ONLY REFRESH CBR REFRESH SELF REFRESH RAS# H L L L L L L L L L L L→H→L L→H→L L H→L H→L CAS# H→X L L L H→L H→L H→L H→L L→H H→L H→L L L H L L WE# X H L H→L H H L L H H→L H→L H L X H H OE# X L X L→H L L X X L L→H L→H L X X X X ADDRESSES tR tC XX ROW COL ROW COL ROW COL ROW COL n/a COL ROW COL n/a COL n/a n/a ROW COL n/a COL ROW COL ROW COL ROW n/a XX XX DATA-IN/OUT DQ1-DQ4 High-Z Data-Out Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z High-Z 4 Meg x 4 EDO DRAM D47.pm5 – Rev. 3/97 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1997, Micron Technology, Inc. 5 Page TECHNOLOGY, INC. 4 MEG x 4 EDO DRAM READ CYCLE tRC tRAS tRP RAS# V IH V IL tCRP tRCD tCSH tRSH tCAS tRRH CAS# V V IH IL ,,,, ,,,, ,, ,ADDR V V IH IL , , ,, , ,,,,,,,,,WE# V IH V IL tASR tRAD tRAH ROW tAR tASC tACH tCAH tRCS COLUMN tAA tRAC tRCH NOTE 1 ROW DQ V V OH OL ,,,,,,,,,,,,,,,,,,,,,,,,,OE# V IH V IL OPEN tCAC tCLZ t OE tOFF VALID DATA t OD OPEN DON’T CARE UNDEFINED TIMING PARAMETERS SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOD tOE -5 MIN MAX 25 12 38 0 0 13 8 8 10,000 0 5 38 0 12 12 -6 MIN MAX 30 15 45 0 0 15 10 10 10,000 0 5 45 0 15 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH -5 MIN MAX 0 12 50 9 9 50 10,000 84 11 0 0 30 0 13 -6 MIN MAX 0 15 60 12 10 60 10,000 104 14 0 0 40 0 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 4 Meg x 4 EDO DRAM D47.pm5 – Rev. 3/97 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1997, Micron Technology, Inc. 11 Page

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