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PDF AT8989UP Data sheet ( Hoja de datos )
| Número de pieza | AT8989UP | |
| Descripción | 9 Port 10/100 Mb/s Single Chip Ethernet Switch Controller | |
| Fabricantes | ATAN | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AT8989UP (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ATAN Technology, Inc.
AT8989UP 9 port 10/100 Mb/s
Single Chip Ethernet Switch Controller
Preliminary Data Sheet
Revision 1.1
Feb 2002
9 port 10/100Mb/s Single Chip Switch Controller
1
Revision 1.1
AT8989UP
1 page  
ATAN Technology, Inc.
2. Pinout
2.1 8 TP/FX PORT+ Expansion/MII/GPSI
PORT 208 Pin Diagram
157 GNDO
158 GNDO
159 VCC3O
160 VCC3O
161 GRXD4
162 GRXD5
163 GRXD6
164 GRXD7
165 GNDO
166 GNDO
167 DUPCOL7
168 DUPCOL6
169 DUPCOL5
170 DUPCOL4 (DUPCOL_P7)
171 GNDO
172 GNDO
173 VCC3O
174 VCC3O
175 DUPCOL3 (DUPCOL_P6)
176 DUPCOL2 (DUPCOL_P4)
177 DUPCOL1 (DUPCOL_P2) (PHYAS1)
178 DUPCOL0 (DUPCOL_P0) (RECANEN)
179 MDC
180 MDIO
181 BONDG
182 VCC2IK
183 VCC2IK
184 VCC2IK
185 GNDIK
186 GNDIK
187 GNDIK
188 RC
189 XI
190 XO
191 VCCPLL
192 GNDPLL
193 GNDPLL
194 CONTROL
195 VREF
196 GNDRG
197 GNDBIAS
198 RTX
199 VCCBIAS
200 VCCRG
201 VCCA2
202 TXP0
203 TXN0
204 GNDA
205 GNDA
206 RXP0
207 RXN0
208 VCCAD
AT8989UP-208
GNDIK
GNDIK
(GFCEN) GTXD0
(P7FX) GTXER
VCC2IK
GTXCLK
GNDIK
GNDIK
GTXD1
GTXD2
GTXD3
GNDO
GNDO
VCC3O
VCC3O
GTXD4
GTXD5
GTXD6
GTXD7
GNDO
GNDO
LDSPD7
LDSPD6
LDSPD5
(SPD_P7) LDSPD4
GNDO
GNDO
VCC3O
VCC3O
(SPD_P6) LDSPD3
(SPD_P4) LDSPD2
VCC2IK
VCC2IK
GNDIK
GNDIK
(SPD_P2) LDSPD1
(SPD_P0) LDSPD0
CFG1
TEST
VCC2IK
VCC2IK
GNDIK
GNDIK
GNDSUBA
VCCA2
TXP7
TXN7
GNDA
GNDA
RXP7
RXN7
VCCAD
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
9 port 10/100Mb/s Single Chip Switch Controller
5
Revision 1.1
AT8989UP
5 Page 
ATAN Technology, Inc.
A/D Converter
Adaptive Equalizer and timing recovery module
NRZI/NRZ and serial/parallel decoder
De-scrambler
Symbol alignment block
Symbol Decoder
Collision Detect Block
Carrier sense Block
Stream decoder block
3.2.2.1 A/D Converter
High performance A/D converter with 125M sampling rate converts signals received on RXP/RXN pins to 6 bits data
streams; besides it possess auto-gain-control capability that will further improve receive performance especially under long
cable or harsh detrimental signal integrity. Due to high pass characteristic on transformer, built in base-line-wander
correcting circuit will cancel it out and restore its DC level.
3.2.2.2 Adaptive Equalizer and timing Recovery Module
All digital design is especial immune from noise environments and achieves better correlation between production and
system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates line loss induced from twisted pair and tracks
far end clock at 125M samples per second. Adaptive Equalizer implemented with Feed forward and Decision Feedback
techniques meet the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 120
meters.
3.2.2.3 NRZI/NRZ and Serial/Parallel Decoder
The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group’s boundary.
3.2.2.4 Data De-scrambling
The de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its
deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization,
the incoming data is XORed by the deciphering LFSR and de-scrambled.
In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it
generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status.
Upon synchronization of the de-scrambler the hold timer starts a 722 us countdown. Upon detection of sufficient idle
symbols within the 722 us period, the hold timer will reset and begin a new countdown. This monitoring operation will
continue indefinitely given a properly operating network connection with good signal integrity. If the link state monitor does
not recognize sufficient unscrambled idle symbols within 722 us period, the de-scrambler will be forced out of the current
state of synchronization and reset in order to re-acquire synchronization.
3.2.2.5 Symbol Alignment
The symbol alignment circuit in the AT8989UP determines code word alignment by recognizing the /J/K delimiter pair.
This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
9 port 10/100Mb/s Single Chip Switch Controller
Revision 1.1
AT8989UP
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT8989UP.PDF ] | |
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