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25PPC405EP 데이터시트 PDF




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25PPC405EP 데이터시트, 핀배열, 회로
Preliminary
PowerPC 405EP Embedded Processor Data Sheet
www.DataSheet4U.com
Features
• IBM PowerPC405 32-bit RISC processor core
operating up to 266MHz with 16KB D- and I-
caches
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
• 4KB on-chip memory (OCM)
• External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8- or 16-bit SRAM and
external peripherals
- Up to five devices
• DMA support for memory and UARTs.
- Scatter-gather chaining supported
- Four channels
- Internal or external PCI Bus Arbiter
• Two Ethernet 10/100Mbps (full-duplex) ports
with media independent interface (MII)
• Programmable interrupt controller supports
seven external and 19 internal edge triggered or
level-sensitive interrupts
• Programmable timers
• Software accessible event counters
• Two serial ports (16750 compatible UART)
• One IIC interface
• General purpose I/O (GPIO) available
• Supports JTAG for board level testing
• Internal processor local Bus (PLB) runs at
SDRAM interface frequency
• PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
- Asynchronous PCI Bus interface
• Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded
applications, the PowerPC 405EP (PPC405EP)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA-27E, 0.18 µm
(0.11 µm Leff)
Package: 31mm, 385-ball, enhanced plastic ball
grid array (E-PBGA)
Power (typical): 1.2W at 200MHz
10/22/02
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
1




25PPC405EP pdf, 반도체, 판매, 대치품
Preliminary
www.DataSheet4U.com
PowerPC 405EP Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local IBM sales office.
Product Name
Order Part Number1
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
PPC405EP IBM25PPC405EP-3AA133C
133MHz 31mm, 385 E-PBGA A 0x51210950 0x20267049
PPC405EP IBM25PPC405EP-3AA133CZ 133MHz 31mm, 385 E-PBGA A 0x51210950 0x20267049
PPC405EP IBM25PPC405EP-3AA200C
200MHz 31mm, 385 E-PBGA A 0x51210950 0x20267049
PPC405EP IBM25PPC405EP-3AA200CZ 200MHz 31mm, 385 E-PBGA A 0x51210950 0x20267049
PPC405EP IBM25PPC405EP-3AA266C
266MHz 31mm, 385 E-PBGA A 0x51210950 0x20267049
PPC405EP IBM25PPC405EP-3AA266CZ 266MHz 31mm, 385 E-PBGA A 0x51210950 0x20267049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die
mask revision number and is specified in the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) is software accessible and contains additional information about the
revision level of the part. Refer to the PowerPC 405EP Embedded Processor User’s Manual for details on the
register content.
Order Part Number Key
IBM25PPC405EP-3AA266Cx
IBM Part Number
Grade 3 Reliability
Shipping Package
Blank = Tray
Z = Tape and reel
Operational Case Temperature
Range (-40 °C to +85 °C)
Processor Speed
266 MHz
Package
31mm, 385 E-PBGA
Revision Level
4 10/22/02

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25PPC405EP 전자부품, 판매, 대치품
PowerPC 405EP Embedded Processor Data Sheet
www.DataSheet4U.com
Preliminary
DCR Address Map 4KB Device Configuration Registers
Function
Start Address
End Address
Size
Total DCR Address Space1
0x000
0x3FF
1KW (4KB)1
By function:
Reserved
0x000
0x00F
16W
Memory Controller Registers
0x010
0x011
2W
External Bus Controller Registers
0x012
0x013
2W
Reserved
0x014
0x017
2W
On-Chip Memory Controller Registers
0x018
0x01F
8W
Reserved
0x020
0x07F
96W
PLB Registers
0x080
0x08F
16W
Reserved
0x090
0x09F
16W
OPB Bridge Out Registers
0x0A0
0x0A7
8W
Reserved
0x0A8
0x0AF
6W
Clock, Control, and Reset
0x0B0
0x0B7
8W
Power Management
0x0B8
0x0BF
8W
Interrupt Controller
0x0C0
0x0CF
16W
Reserved
0x0D0
0x0FF
48W
DMA Controller Registers
0x100
0x13F
64W
Reserved
0x140
0x17F
64W
Ethernet MAL Registers
0x180
0x1FF
128W
Event Counters
0x200
0x203
4W
Reserved
0x204
0x3FF
508W
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single
32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
10/22/02
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