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PDF ST10R172L Data sheet ( Hoja de datos )
| Número de pieza | ST10R172L | |
| Descripción | 16-BIT LOW VOLTAGE ROMLESS MCU | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST10R172L
16-BIT LOW VOLTAGE ROMLESS MCU
s High Performance 16-bit CPU
q CPU Frequency: 0 to 50 MHz
q 40ns instruction cycle time at 50-MHz CPU
clock
q 4-stage pipeline
q Register-based design with multiple
variable register banks
q Enhanced boolean bit manipulation
facilities
q Additional instructions to support HLL and
operating systems
q Single-cycle context switching support
q 1024 bytes on-Chip special function
register area
s Memory Organisation
q 1KByte on-chip RAM
q Up to 16 MBytes linear address space for
code and data (1 MByte with SSP used)
s External Memory Interface
q Programmable external bus characteristics
for different address ranges
q 8-bit or 16-bit external data bus
q Multiplexed or demultiplexed external
address/data buses
q Five programmable chip-select signals
q Hold and hold-acknowledge bus arbitration
support
s One Channel PWM Unit
s Fail Safe Protection
q Programmable watchdog timer
q Oscillator Watchdog
s Interrupt
q 8-channel interrupt-driven single-cycle data
transfer facilities via peripheral event
controller (PEC)
q 16-priority-level interrupt system with 17
sources, sample-rate down to 40 ns
s Timers
PRODUCT PREVIEW
Depdiincsated P.6
P.4
P.1
OSC WDT
XSSP
PLL
DPRAM
ST10 CORE
Interrupt Controller
&PEC
ASC GPT1/2 PWM
P.0
P.3 P.5
P.7 Po.2
q Two multi-functional general purpose timer
units with 5 timers
q Clock Generation via on-chip PLL, or via
direct or prescaled clock input
s Serial Channels
q Synchronous/asynchronous
q High-speed-synchronous serial port SSP
s Up to 77 general purpose I/O lines
s No bootstrap loader
s Electrical Characteristics
q 5V Tolerant I/Os
q 5V Fail-Safe Inputs (Port 5)
q Power: 3.3 Volt +/-0.3V
q Idle and power down modes
s Support
q C-compilers, macro-assembler packages,
emulators, evaluation boards, HLL-
debuggers, simulators, logic analyser
disassemblers, programming boards
s Package
q 100-Pin Thin Quad Flat Pack (TQFP)
April 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
Rev. 1.1
1/68
1
1 page  
ST10R172L - PIN DESCRIPTION
P5.10
–P5.15
98-100
1- 3
98
I
I
I
99 I
100 I
1I
2I
3I
XTAL1 5
I
XTAL2 6
O
5S 6-bit input-only port with Schmitt-Trigger characteristics.
5S Port 5 pins also serve as timer inputs:
5S P5.10
T6EUD
GPT2 Timer T6 Ext.Up/Down
Ctrl.Input
5S P5.11
T5EUD
GPT2 Timer T5 Ext.Up/Down
Ctrl.Input
5S P5.12
T6IN
GPT2 Timer T6 Count Input
5S P5.13
T5IN
GPT2 Timer T5 Count Input
5S P5.14
T4EUD
GPT1 Timer T4 Ext.Up/Down
Ctrl.Input
5S P5.15
T2EUD
GPT1 Timer T2 Ext.Up/Down
Ctrl.Input
3T XTAL1: Input to the oscillator amplifier and internal clock
generator
3T XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Observe minimum and maximum high/low and
rise/fall times specified in the AC Characteristics.
Table 1 Pin definitions
5/68
1
5 Page 
ST10R172L - FUNCTIONAL DESCRIPTION
2 FUNCTIONAL DESCRIPTION
ST10R172L architecture combines the advantages of both RISC and CISC processors with
an advanced peripheral subsystem. The following block diagram overviews the different on-
chip components and the internal bus structure.
XTAL1
XTAL2
EA, ALE, RD,
WR/WRL,
READY, NMI,
RSTIN,
RSTOUT
I/O
CS(4:0)
HOLD
HLDA
BREQ
I/O
A(23:16),
SSPCLK,
SSPDAT,
SSPCE(1:0)
I/O
I/O, D(7:0)
I/O
A(15:0)
D(15:8), D(7:0)
A(15:8), AD(7:0)
AD(15:8), AD(7:0)
dedicated
pins
Port 6
8-bit
Port 4
8-bit
Port 1
2x8-bit
Port 0
2x8-bit
OSC
WDT
PLL
1KByte
DPRAM
XSSP
4-bit
ST10 CORE
ASC
Interrupt Controller
& PEC
GPT1/2
PWM
Port 3
15-bit
Port 5
6-bit
Port 7
4-bit
Port 2
4-bit
I/O
CLKOUT,
BHE/WRH, RxD0,
TxD0, T2IN, T3IN,
T4IN, T3EUD,
T3OUT, CAPIN,
T6OUT
I
T2EUD,
T4EUD, T5IN,
T6IN, T5EUD,
T6EUD
I/O
POUT3
I/O
EXIN(3:0)
Figure 2 Block diagram
11/68
1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST10R172L.PDF ] | |
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