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PDF AD9512 Data sheet ( Hoja de datos )
| Número de pieza | AD9512 | |
| Descripción | 1.2 GHz Clock Distribution IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1.2 GHz Clock Distribution IC, 1.6 GHz Inputs,
Dividers, Delay Adjust, Five Outputs
AD9512
FEATURES
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
FUNCTION
DSYNC
DSYNCB
CLK1
CLK1B
CLK2
CLK2B
SCLK
SDIO
SDO
CSB
FUNCTIONAL BLOCK DIAGRAM
VS GND RSET
SYNCB,
RESETB
PDB
DETECT
SYNC
SERIAL
CONTROL
PORT
VREF
AD9512
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
/1, /2, /3... /31, /32
SYNC
STATUS
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVDS/CMOS
/1, /2, /3... /31, /32
LVDS/CMOS
ΔT
DELAY
ADJUST
SYNC
STATUS
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B
OUT3
OUT3B
OUT4
OUT4B
Figure 1.
GENERAL DESCRIPTION
The AD9512 provides a multi-output clock distribution in a
design that emphasizes low jitter and low phase noise to
maximize data converter performance. Other applications with
demanding phase noise and jitter requirements can also benefit
from this part.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that may be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output may be varied by means
of a divider phase select function that serves as a coarse timing
adjustment.
One of the LVDS/CMOS outputs features a programmable
delay element with a range of up to 10 ns of delay. This fine
tuning delay block has 5-bit resolution, giving 32 possible delays
from which to choose.
The AD9512 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9512 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. The temperature range is
−40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9512
SPECIFICATIONS
Typical (Typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max)
values are given over full VS and TA (−40°C to +85°C) variation.
CLOCK INPUTS
Table 1.
Parameter
CLOCK INPUTS (CLK1, CLK2)1
Input Frequency
Input Sensitivity
Input Level
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Min Typ Max Unit
Test Conditions/Comments
0 1.6
1502
23
1.5 1.6 1.7
1.3 1.8
150
4.0 4.8 5.6
2
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Jitter performance can be improved with higher slew
rates (greater swing).
Larger swings turn on the protection diodes and can
degrade jitter performance.
Self-biased; enables ac coupling.
With 200 mV p-p signal applied; dc-coupled.
CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
Self-biased.
1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
2 With a 50 Ω termination, this is −12.5 dBm.
3 With a 50 Ω termination, this is +10 dBm.
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2; Differential
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
LVDS CLOCK OUTPUTS
OUT3, OUT4; Differential
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUTS
OUT3, OUT4
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
Min
VS − 1.22
VS − 2.10
660
250
1.125
Typ
VS − 0.98
VS − 1.80
810
360
1.23
14
Max
1200
VS − 0.93
VS − 1.67
965
800
450
25
1.375
25
24
Unit Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
MHz See Figure 14
V
V
mV
Termination = 100 Ω differential; default
Output level 40h (41h)<2:1> = 01b
3.5 mA termination current
MHz See Figure 15
mV
mV
V
mV
mA Output shorted to GND
VS − 0.1
Single-ended measurements;
B outputs: inverted, termination open
250 MHz With 5 pF load each output; see Figure 16
V @ 1 mA load
0.1 V @ 1 mA load
Rev. A | Page 4 of 48
5 Page 
AD9512
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz
Any LVPECL (OUT0 to OUT2) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz
Any LVPECL (OUT0 to OUT2) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 100 MHz
Both LVDS (OUT3, OUT4) = 100 MHz
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both LVDS (OUT3, OUT4) = 50 MHz
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off)
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On)
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
LVDS (OUT4) = 50 MHz
All LVPECL = 50 MHz
Min Typ Max Unit Test Conditions/Comments
40 fs rms BW = 12 kHz − 20 MHz (OC-12)
55 fs rms BW = 12 kHz − 20 MHz (OC-3)
215 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
215 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
222 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
225 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
225 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
264 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
319 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
395 fs rms Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Rev. A | Page 10 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9512.PDF ] | |
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