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PDF LXT3008 Data sheet ( Hoja de datos )
| Número de pieza | LXT3008 | |
| Descripción | T1/E1/J1 N+1 Protection Interface Unit | |
| Fabricantes | Intel | |
| Logotipo |  |
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LXetT43U0.c0o8mT1/E1/J1 N+1 Protection Interface Unit
She Preliminary Datasheet
ta The Intel® Protection Interface Unit (Intel® PIU), LXT3008, is a multiplexing element to be used
a in lieu of relays for more reliable and faster switching in a protection environment. It
.D incorporates eight receivers and eight drivers in a single 160 ball PBGA package. The PIU is
w used in an N+1 redundancy scheme for Short Haul (SH) applications. It is used in conjunction
w with the Intel® LXT38x family of Line Interface Units (LIUs).
w Each PIU contains eight three-state drivers and high impedance receivers. On the analog side,
mthese devices interface to the primary T1/E1 bus and can either drive it or stay in a non-intrusive,
high impedance state. On the digital side, the PIU provides recovered clock and data and also
oaccepts transmit input clock and data. The receive output clock and data signals can be tri-stated.
Therefore, multiple PIU elements can be connected in parallel.
.cIntel PIUs are controlled by hardware and therefore require no dedicated microprocessor. A 1x
reference clock (1.544 MHz for T1 and 2.048 MHz for E1) is required for clock recovery. A
single reference clock can feed all the PIUs in a protection matrix. Both the output analog drivers
Uand the receive clock and data digital buffers can be tri-stated. PIUs also include three line build-
out inputs (LEN0-2) for T1 DSX applications.
t4For further information on N+1 Protection, please see Application Note: N+1 Protection
Without Relays Using Intel® Protection Interface Units (Intel® PIUs) - Intel® LXT3008 for T1/
eE1/J1 (Order Number 249532).
es LOS per ITU G.775, ETS 300 233 and
hT1.231
s 4 wire serial control interface
Ss Hardware or serial host control mode
taLXT3008 Block Diagram
s JTAG Boundary Scan test port per IEEE
1149.1
s 160 ball PBGA package
s Tri-stateable analog and digital short haul
interface
aANALOG
.D DRIVER
x8
DIGITAL TX
INTERFACE
ww ANALOG
mRECEIVER
w ox8
et4U.cHARDWARE OR
eSERIAL CONTROL
www.DataShINTERFACE
DIGITAL RX
INTERFACE
TIMING
Order Number: 249531-003
June 2001
1 page  
T1/E1/J1 N+1 Protection Interface Unit — LXT3008
25 Reserved, RSVD (13h)........................................................................................31
26 Reserved, RSVD (14h)........................................................................................31
27 Reserved, RSVD (15h)........................................................................................31
28 TAP State Description .........................................................................................33
29 Boundary Scan Register (BSR)...........................................................................35
30 Analog Port Scan Register (ASR) .......................................................................38
31 Instruction Register (IR) ......................................................................................39
32 Absolute Maximum Ratings.................................................................................40
33 Recommended Operating Conditions .................................................................40
34 DC Characteristics ..............................................................................................41
35 E1 Transmit Transmission Characteristics..........................................................42
36 E1 Receive Transmission Characteristics...........................................................42
37 T1 Transmit Transmission Characteristics ..........................................................43
38 T1 Receive Transmission Characteristics ...........................................................44
39 Analog Test Port Characteristics.........................................................................45
40 Transmit Timing Characteristics..........................................................................45
41 Receive Timing Characteristics...........................................................................46
42 JTAG Timing Characteristics...............................................................................46
43 Serial I/O Timing Characteristics.........................................................................47
44 G.703 2.048 Mbps Pulse Mask Specifications ....................................................48
45 T1.102 1.544 Mbps Pulse Mask Specifications...................................................49
Prelininary Datasheet
5
5 Page 
LXT3008 — T1/E1/J1 N+1 Protection Interface Unit
Table 1. LXT3008 Pin Description (Sheet 2 of 7)
Ball #
PBGA
A6, B6
P1
P2
P3
N1
N2
N3
Symbol
TGND7
RCLK0
RPOS0
RNEG0
TCLK0
TPOS0
TNEG0
I/O1 Description
S Transmit Driver Ground.
Digital Interface Connections.
Receive Clock Output.
DO This pin provides the recovered clock from the signal received at RTIP and
RRING. Under LOS conditions there is a transition from RCLK signal (derived
from the recovered data) to MCLK signal at the RCLK output.
Receive Positive Data.
Receive Negative Data.
Bipolar Mode:
These pins act as active High bipolar Non Return to Zero (NRZ) receive
signal outputs. A High signal on RPOS corresponds to receipt of a positive
DO
pulse on RTIP/RRING. A High signal on RNEG corresponds to receipt of a
negative pulse on RTIP/RRING. These signals are valid on the falling or rising
DO edges of RCLK depending on the CLKE input.
Hardware Mode:
During a LOS condition, RPOS and RNEG will remain active.
Serial Host Mode:
RPOS and RNEG will either remain active or insert AIS into the receive path.
Selection is determined by the RAISEN bit in the GCR register.
Transmit Clock Input. During normal operation TCLK is active, and TPOS
and TNEG are sampled on the falling edge of TCLK. If TCLK is Low, the
output drivers enter a low power high-Z mode. If TCLK is High for more than
16 clock cycles, the pulse shaping circuit is disabled and the transmit output
pulse widths are determined by the TPOS and TNEG duty cycles.
TCLK
Operating Mode
DI Clocked Normal operation
L Driver outputs enter tri-state
When pulse shaping is disabled, it is possible to overheat and damage the
LXT3008 device by leaving transmit inputs high continuously. For example, a
programmable ASIC might leave all outputs high until it is programmed. To
prevent this, clock one of these signals: TPOS, TNEG, TCLK or MCLK.
Another solution is to set one of these signals low: TPOS, TNEG, TCLK, or
OE.
Transmit Positive Data Input.
Transmit Negative Data Input.
Bipolar Mode:
TPOS/TNEG are active High NRZ inputs. TPOS indicates the transmission of
a positive pulse, whereas TNEG indicates the transmission of a negative
pulse.
DI
DI
TPOS
TNEG
Selection
0 0 Space
1 0 Positive Mark
0 1 Negative Mark
1 1 Space
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
Preliminary Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT3008.PDF ] | |
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