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PDF ADSP21990 Data sheet ( Hoja de datos )
| Número de pieza | ADSP21990 | |
| Descripción | Mixed Signal DSP Controller | |
| Fabricantes | Analog Devices | |
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PRELIMINARY TECHNICAL DATA
aPrelitamSinheaeryt4TUe.ccohmnical Data Mixed Signal DASDPSPC-o2n1t9r9o0llerMIXED SIGNAL DSP CONTROLLER FEATURES
ADSP-219x, 16-bit, Fixed Point DSP Core with up to 160
aMIPS sustained performance
.D8K Words of On chip RAM, Configured as 4K Words On
wchip 24-bit Program RAM and 4K Words On chip 16-bit
Data RAM
w External Memory Interface
w Dedicated Memory DMA Controller for Data/Instruction
mTransfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
oCircuitry Enables Full speed Operation from Low
speed Input Clocks
.cIEEE JTAG Standard 1149.1 Test Access Port Supports
On chip Emulation and System Debugging
8-Channel, 20 MSPS, 14-bit Analog to Digital Converter
USystem
Three Phase 16-bit Center Based PWM Generation Unit
with 12.5 ns resolution
Dedicated 32-bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-bit Auxiliary PWM Outputs
16 General Purpose Flag I/O Pins
Three Programmable 32-bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0V Voltage Reference
Integrated Power-On-Reset (POR) Generator
t4FUNCTIONAL BLOCK DIAGRAM
SheeJTAG
TEST &
taEMULATION
CLOCK
GENERATOR / PLL
160 MHZ
ADSP-219X
DSP
aI/O
BUS
w.DI/O REGISTERS
4K X 24
PM RAM
(BLOCK 0)
4K X 16
DMRAM
(BLOCK 1)
4K X 24
PMROM
(BLOCK 2)
PM ADDRESS/DATA
DM ADDRESS/DATA
EXTERNAL
MEMORY
INTERFACE
(EMI)
ADDRESS
DATA
CONTROL
MEMORY DMA
CONTROLLER
ww omTIMER0
ADC CONTROL
PWM
ENCODER AUXILIARY
INTERRUPT
.cGENERATION INTERFACE
PWM
TIMER 1
FLAG
SPI
SPORT
WATCHDOG CONTROLLER
UUNIT
UNIT
(AND EET)
UNIT
TIMER 2
I/O
TIMER
(ICNTL)
PIPELINE
t4FLASH ADC
heePOR
VREF
ataSREV. PrA
w.DThis information applies to a product under development. Its characteristics and specifi- One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
cations are subject to change without notice. Analog Devices assumes no obligation Tel:781/329-4700
www.analog.com
wwregarding future manufacturing unless otherwise agreed to in writing.
Fax:781/326-8703
©Analog Devices,Inc., 2002
1 page  
PRELIMINARY TECHNICAL DATA
February 2002
For current information contact Analog Devices at (781) 937-1799
ADSP-21990
0X000000
0X000FFF
0X001000
0X007FFF
0X008000
0X008FFF
0X009000
0X00FFFF
0X010000
0X400000
0X800000
0XC00000
0XFF0000
0XFF0FFF
0XFF1000
0XFFFFFF
BLOCK 0: 4K X 24-BIT RAM
RESERVED (28K)
BLOCK 1: 4K X 16-BIT RAM
RESERVED (28K)
EXTERNAL MEMORY
(4M - 64K)
EXTERNAL MEMORY
EXTERNAL MEMORY
EXTERNAL MEMORY
(4M - 64K)
BLOCK 2: 4K X 24-BIT
PM ROM
UNUSED ON-CHIP
MEMORY (60K)
PAGE 0 (64K) ON-CHIP
(0 WAIT STATE)
PAGES 1 TO 63
BANK 0 (OFF-CHIP)
MS0
PAGES 64 TO 127
BANK 1 (OFF-CHIP)
MS1
PAGES 128 TO 191
MS2
BANK 2 (OFF-CHIP)
PAGES 192 TO 254
BANK 0 (OFF-CHIP) MS3
PAGE 255
(ON-CHIP
Figure 2. ADSP-21990 DSP Core Memory Map at Reset
NOTE: The physical external memory addresses are limited
by 20 address lines, and are determined by the external data
width and packing of the external memory space. The
Strobe signals (MS3 - 0) can be programmed to allow the
user to change starting page addresses at run time.
Internal (On chip) Memory
The ADSP-21990’s unified program and data memory
space consists of 16M locations that are accessible through
two 24-bit address buses, the PMA and DMA buses. The
DSP uses slightly different mechanisms to generate a 24-bit
address for each bus. The DSP has three functions that
support access to the full memory map.
• The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page. The DMPG1 register is also
used as a page register when accessing external memory.
The program must set DMPG1 accordingly, when
accessing data variables in external memory. A 'C'
program macro is provided for setting this register.
• The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
• For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
The ADSP-21990 has 4K word of on chip ROM that holds
boot routines. The DSP starts executing instructions from
the on chip boot ROM, which starts the boot process. For
more information, see Booting Modes on page 13. The on
chip boot ROM is located on Page 255 in the DSP’s
memory space map, starting at address 0xFF0000.
External (Off Chip) Memory
Each of the ADSP-21990’s off chip memory spaces has a
separate control register, so applications can configure
unique access parameters for each space. The access param-
eters include read and write wait counts, wait state
completion mode, I/O clock divide ratio, write hold time
extension, strobe polarity, and data bus width. The core
clock and peripheral clock ratios influence the external
memory access strobe widths. For more information, see
Clock Signals on page 12. The off chip memory spaces are:
• External memory space (MS3–0 pins)
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of these off chip memory spaces are accessible through
the External Port, which can be configured for 8-bit or
16-bit data widths.
External Memory Space
External memory space consists of four memory banks.
These banks can contain a configurable number of 64 k
Word pages. At reset, the page boundaries for external
memory have Bank0 containing pages 1 to 63, Bank1 con-
taining pages 64 to 127, Bank2 containing pages 128 to 191,
and Bank3 containing pages 192 to 254. The MS3-MS0
memory bank pins select Banks 3-0, respectively. Both the
ADSP-219x core and DMA capable peripherals can access
the DSP’s external memory space.
All accesses to external memory are managed by the
External Memory Interface Unit (EMI).
I/O Memory Space
The ADSP-21990 supports an additional external memory
called I/O memory space. The IO space consists of 256
pages, each containing 1024 addresses. This space is
designed to support simple connections to peripherals (such
as data converters and external registers) or to bus interface
ASIC data registers. The first 32K addresses (IO pages 0 to
31) are reserved for on chip peripherals. The upper 224k
REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
5
5 Page 
PRELIMINARY TECHNICAL DATA
February 2002
For current information contact Analog Devices at (781) 937-1799
ADSP-21990
General Purpose Timers
The ADSP-21990 contains a general purpose timer unit
that contains three identical 32-bit timers. The three pro-
grammable interval timers (Timer0, Timer1 and Timer2)
generate periodic interrupts. Each timer can be indepen-
dently set to operate in one of three modes:
• Pulse Waveform Generation (PWM_OUT) mode
• Pulse Width Count/Capture (WDTH_CAP) mode
• External Event Watchdog (EXT_CLK) mode
Each Timer has one bidirectional chip pin, TMR2-TMR0.
For each timer, the associated pin is configured as an output
pin in PWM_OUT Mode and as input pin in WDTH_CAP
and EXT_CLK Modes.
Interrupts
The interrupt controller lets the DSP respond to 17 inter-
rupts with minimum overhead. The DSP core implements
an interrupt priority scheme as shown in Table 2. Applica-
tions can use the unassigned slots for software and
peripheral interrupts. The Peripheral Interrupt Controller
is used to assign the various peripheral interrupts to the 12
user assignable interrupts of the DSP core.
Table 2. Interrupt Priorities/Addresses
Interrupt
Emulator (NMI)
—Highest Priority
Reset (NMI)
Power Down (NMI)
Loop and PC Stack
Emulation Kernel
User Assigned Interrupt
(USR0)
User Assigned Interrupt
(USR1)
User Assigned Interrupt
(USR2)
User Assigned Interrupt
(USR3)
User Assigned Interrupt
(USR4)
User Assigned Interrupt
(USR5)
User Assigned Interrupt
(USR6)
User Assigned Interrupt
(USR7)
User Assigned Interrupt
(USR8)
IMASK/
IRPTL
NA
Vector Address
NA
0 0x00 0000
1 0x00 0020
2 0x00 0040
3 0x00 0060
4 0x00 0080
5 0x00 00A0
6 0x00 00C0
7 0x00 00E0
8 0x00 0100
9 0x00 0120
10 0x00 0140
11 0x00 0160
12 0x00 0180
Table 2. Interrupt Priorities/Addresses (Continued)
Interrupt
User Assigned Interrupt
(USR9)
User Assigned Interrupt
(USR10)
User Assigned Interrupt
(USR11)
—Lowest Priority
IMASK/
IRPTL
13
Vector Address
0x00 01A0
14 0x00 01C0
15 0x00 01E0
There is no assigned priority for the peripheral interrupts
after reset. To assign the peripheral interrupts a different
priority, applications write the new priority to their corre-
sponding control bits (determined by their ID) in the
Interrupt Priority Control register.
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially.
Interrupts can be masked or unmasked with the IMASK
register. Individual interrupt requests are logically ANDed
with the bits in IMASK; the highest priority unmasked
interrupt is then selected. The emulation, power down, and
reset interrupts are nonmaskable with the IMASK register,
but software can use the DIS INT instruction to mask the
power down interrupt.
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
The IRPTL register is used to force and clear interrupts.
On chip stacks preserve the processor status and are auto-
matically maintained during interrupt handling. To support
interrupt, loop, and subroutine nesting, the PC stack is
33 levels deep, the loop stack is eight levels deep, and the
status stack is 16 levels deep. To prevent stack overflow, the
PC stack can generate a stack level interrupt if the PC stack
falls below three locations full or rises above 28
locations full.
The following instructions globally enable or disable
interrupt servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG
and computational registers exist. Switching between the
primary and secondary registers lets programs quickly
service interrupts, while preserving the state of the DSP.
Peripheral Interrupt Controller
The Peripheral Interrupt Controller is a dedicated periph-
eral unit of the ADSP-21990 (accessed via IO mapped
registers). The function of the peripheral interrupt control-
ler is to manage the connection of up to 32 peripheral
interrupt requests to the DSP core.
REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
11
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