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PDF CXD2559 Data sheet ( Hoja de datos )
| Número de pieza | CXD2559 | |
| Descripción | 1-Bit D/A Converter For Audio Application | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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® HI2559, CXD2559
October 1997
Features
NOT
RECOMMENDED
FOR
NEW
DESIGNS
1-Bit D/A Converter
Description
For
Audio
Application
• Two-Channel D/A Converter and Oversampling Digital
Filter Into a Single Chip
• Distortion . . . . . . . . . . . . . . . . . . . . . . . . 0.012% or Less
• S/N Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB or More
• Master Clock . . . . . . . . . . . . . . . . . . . . . 384FS or 256FS
The HI2559, CXD2559 is a 1-bit stereo D/A converter featur-
ing a 2nd-order ∆∑ system noise shaper. This good cost per-
formance LSI has functions such as digital attenuator and
digital de-emphasis and others.
Ordering Information
Applications
• CD Player and CD-ROM Player, etc.
Functions
• Data Can Be Input at Rate of 1 x FS with a Built-In Digital
Filter
• The 24-/32-Slot Serial Data Interface Enables
Independent Selection of Data Frontward Trunca-
tion/Rearward Truncation and MSB First/LSB First
• Two Channels Can Be Attenuated Independently in 255
Steps
• The Output From Two Channels (L/R/L + R/Mute) Can
Be Selected Independently
• Digital Emphasis
PART
NUMBER
HI2559JCQ
CXD2559Q
TEMP.
RANGE (oC)
-20 to 75
-20 to 75
PACKAGE
32 Ld MPQF
32 Ld MPQF
PKG. NO.
Q32.7x7-S
Q32.7x7-S
Pinout
HI2559, CXD2559
(MQFP)
TOP VIEW
AVDD0
AOUT2-
AVSS0
DVDD0
TEST
CLR
MASL
DVSS0
1
3231
30
29
28
27
26
25
24
2 23
3 22
4 21
5 20
6 19
7 18
89
10
11
12
13
14
15
17
16
AVDD1
AOUT1-
AVSS1
DVSS1
XCLK
DASL0
DASL1
DVDD1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
4-1
File Number 4120.1
1 page  
HI2559, CXD2559
AC Electrical Specifications
PARAMETER
VDD = 5.0 ±10%, TOPR = -20oC to 75oC
SYMBOL
External Clock Pulse Input
Low Level Width
256 FS
384 FS
tCWL
External Clock Pulse Input
Pulse Cycle (Note 2)
256 FS
384 FS
tCYC
Input BCK Frequency
fBCK
Input BCK Pulse Width
tWIB
Input Data Setup Time
tIDS
Input Data Hold Time
tIDH
Input LRCK Setup Time
tILRS
Input LRCK Hold Time
tILRH
Program Input Basic Time
tPR
Latch Input Pulse Width
tWLT
ATT Setup Time
tSET
ATT Hold Time
tHOLD
ATT Interval
tINT
NOTE:
11. Always input an external clock after turning the power on.
38 - 250 ns
25 - 250 ns
76 - 500 ns
50 - 500 ns
- - 3.1 MHz
100 -
- ns
10 -
- ns
15 -
- ns
10 -
- ns
15 -
- ns
100 -
- ns
200 -
- ns
5 - - ns
100 -
- ns
300 -
- ns
ANALOG CHARACTERISTICS
MEASUREMENT CONDITIONS
S/N
THD + N
Dynamic Range
Channel Separation
Output Level
Gain Difference Between Channels
NOTES:
12. A-weighting filter used.
13. -60dB, 1kHz input.
TA = 25oC, VDD = 5.0V, FS = 44kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz,
Master Clock 384FS.
(EIAJ) *1
96 100
-
dB
(EIAJ)
- 0.010 0.012
%
(EIAJ) *1, *2
91 93
-
dB
(EIAJ)
- 90 -
dB
- 2.58 - V (ms)
- - 0.1 dB
4-5
5 Page 
Application Circuit
4-11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CXD2559.PDF ] | |
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