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PDF PLL205-54 Data sheet ( Hoja de datos )
| Número de pieza | PLL205-54 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL205-54 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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om PLL205-54Preliminary
.cProgrammable Clock Generator for VIA KT-266 Chipset
t4UFEATURES
ee• Generates all clock frequencies for VIA KT266
hchipset.
taS• Support one pair of differential CPU clocks, one
apair of differential push-pull CPU clocks, 3 AGP
.Dand 10 PCI.
w• Enhanced PCI Output Drive selectable by I2C.
w• One 48MHz clock and 24_48MHz clock via I2C.
w• Three 14.318MHz reference clocks.
m• Program 5-bit CPU VID (Voltage Identification)
through I2C.
o• Power management control to stop CPU, PCI,
.cREF, 24_48MHz, 48MHz and AGP clocks.
• Supports 2-wire I2C serial bus interface with
Ureadback.
• Single byte micro-step linear Frequency
t4Programming via I2C with glitch free smooth
switching.
e• Built-in programmable watchdog timer.
e• Spread Spectrum ±0.25% center, ±0.5% center,
±0.75% center, and 0 to -0.5% downspread.
h• 50% duty cycle with low jitter.
S• Available in 300 mil 48 Pin SSOP.
PIN CONFIGURATION
VDD1
GND
XIN
XOUT
VDD2
48MHz/FS3*^
24_48Mhz/FS4*v
GND
PCI_F
PCI0
PCI1
GND
PCI2
PCI3
VDD3
PCI4
PCI5
PCI6
GND
PCI7
PCI8/FS2*^
PCI9_E/SELPCI9_E#
VDD3
SEL24_48#^
VIDENB^
VID0^
VID1^
VID2^
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF0/FS0*^
55 REF1/FS1*^
54 REF_F
53 REF_STOP#^
52 AGP_STOP#^
51 GND
50 CPUT0
49 CPUC0
48 VDDL1
47 CPUT_CS
46 CPUC_CS
45 GND
44 CPU_STOP#^
43 PCI_STOP/WDRESET#
42 PD#
41 VDDL2
40 GND
39 SDATA
38 SCLK
37 GND
36 AGP2
35 AGP1
34 AGP0
33 VDD4
32 GND
31 VDD5
30 VID4^
29 VID3^
Note: ^: Pull up v: Pull down #: Active low
*: Bi-directional up latched at power-up
taBLOCK DIAGRAM
aXIN
XOUT
XTAL
OSC
w.DFS (0:4)*
ww mPLL1
oSST
Control
Logic
t4U.cPD
SheePLL2
ataSDATA
.DSCLK
÷2
Registers
VDD1
REF(0:1)
REF_F
CPUT0
CPUC0
VDDL1
CPUT_CS
CPUC_CS
VDD4
AGP (0:2)
VDD3
PCI (0:8)
PCI9_E
VDD2
48MHz
24_48MHz
VID (0:4)
POWER GROUP
• VDD1: REF(0:1), REF_F, XIN, XOUT
• VDD2: 48MHz or 24_48MHz
• VDD3: PCI(0:8), PCI9_E
• VDD4: AGP(0:2)
• VDD5: I2C, VID
• VDDL1: CPUT0, CPUC0, CPUT_CS, CPUC_CS
• VDDL2: PLL Core
KEY SPECIFICATIONS
• CPU Cycle to Cycle jitter: 250ps.
• PCI Cycle to Cycle jitter: 500ps.
• PCI to PCI skew: 500ps.
• CPU to CPU skew: 175ps.
• AGP to AGP skew: 250ps.
www47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/04/00 Page 1
1 page  
Preliminary PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
I2C BUS CONFIGURATION SETTING
Address Assignment
Slave
Receiver/Transmitter
Data Transfer Rate
Serial Bits Reading
A6 A5 A4 A3 A2 A1 A0 R/W
11
0
1001
_
Provides both slave write and readback functionality
Standard mode at 100kbits/s
The serial bits will be read or sent by the clock driver in the following order
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
-
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
Data Protocol
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte.
I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
Bit 7 6
0 FS3 ( see Frequency selection Table )
Bit 6 21
0 FS2 ( see Frequency selection Table )
Bit 5 55
0 FS1 ( see Frequency selection Table )
Bit 4 56
0 FS0 ( see Frequency selection Table )
Bit 3 -
0 Frequency selection control bit 1=Via I2C, 0=Via External jumper
Bit 2 7
0 FS4 ( see Frequency selection Table )
Bit 1 -
1 0 = OFF, 1 = Spread Spectrum Enable
Bit 0 -
0 0 = Normal, 1 = Tristate Mode for all outputs
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/04/00 Page 5
5 Page 
Preliminary PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
Junction Temperature
ESD Voltage
VDD VSS-0.5
7
V
VI
VSS-0.5
VDD+0.5
V
VO
VSS-0.5
VDD+0.5
V
TS -65 150 °C
TA 0 70 °C
TJ 115 °C
2 KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. DC/AC Electrical Specifications
PARAMETERS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Supply Current
Transition Time
Pull-up resistor
Pull-down resistor
Input frequency
Input Capacitance
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD
IDDL
IDD
IDDL
Ttrans
RPu
Rdw
FI
CIN
CINX
CONDITIONS
All Inputs except XIN
All inputs except XIN
VIN = VDD
VIN=0 with no pull-up resistor
VIN=0 with pull-up resistor
CL=0 pF@66MHz, 3.3V±5%
CL=0 pF@133MHz, 3.3V±5%
CL=0 pF@66MHz, 2.5V±5%
CL=0 pF@133MHz, 2.5V±5%
To 1st crossing of target Freq.
Pin 6,21,35,36,44,45,47,48
Pin 7
VDD = 3.3V
Logic Inputs
XIN & XOUT pins
MIN.
2
VSS-0.3
-5
-200
12
27
TYP.
MAX. UNITS
VDD+0.3
0.8
V
V
5 uA
uA
120
120
14.318
28
180
72
100
3
16
5
45
mA
ms
kohm
kohm
MHz
pF
pF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/04/00 Page 11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PLL205-54.PDF ] | |
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