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PDF WJLXT972A Data sheet ( Hoja de datos )
| Número de pieza | WJLXT972A | |
| Descripción | Single-Port 10/100 Mbps PHY Transceiver | |
| Fabricantes | Intel | |
| Logotipo |  |
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taShIPenHetteY4l TLraXnTs9c7e2iAveSr ingle-Port 10/100 MbpsDatasheet
.Da The Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver (called hereafter the
w LXT972A Transceiver) directly supports both 100BASE-TX and 10BASE-T applications. The
w LXT972A Transceiver is IEEE compliant and provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT972A Transceiver
w supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the
mLXT972A Transceiver can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A Transceiver is fabricated with an advanced CMOS process and requires only a
osingle 2.53.3 V power supply with 2.5 V MII interface support.
.cApplications
■ Combination 10BASE-T/100BASE-TX
UNetwork Interface Cards (NICs)
■ Network printers
■ 10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
■ Cable Modems and Set-Top Boxes
t4Product Features
e■ 3.3 V Operation
e■ Low power consumption (300 mW typical)
h■ 10BASE-T and 100BASE-TX using a
single RJ-45 connection
■ IEEE 802.3-compliant 10BASE-T or
S100BASE-TX ports with integrated filters
ta■ Auto-negotiation and parallel detection
■ MII interface with extended register
capability
a■ Robust baseline wander correction
■ Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
■ JTAG boundary scan
■ MDIO serial port or hardware pin
configurable
■ Integrated, programmable LED drivers
■ 64-Pin Low-profile Quad Flat Package
(LQFP)
— LXT972ALC - Commercial (0° to 70 °C
ambient)
www.D .DataSheet4U.comDocument Number: 249186-004
www Revision Date: 25-Oct-2005
1 page  
Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver
Figures
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Intel® LXT972A Transceiver Block Diagram ...................................................... 12
Pins for Intel® LXT972A Transceiver 64-Pin LQFP Package ............................. 13
Management Interface Read Frame Structure ................................................... 28
Management Interface Write Frame Structure ................................................... 28
Intel® LXT972A Transceiver MII Interrupt Logic ................................................. 29
Initialization Sequence for Intel® LXT972A Transceiver...................................... 32
Intel® LXT972A Transceiver Link Establishment Overview.................................36
Clocking for 10BASE-T ...................................................................................... 39
Clocking for 100BASE-X .................................................................................... 39
Clocking for Link Down Clock Transition ............................................................ 40
Intel® LXT972A Transceiver Loopback Paths ....................................................42
100BASE-X Frame Format ................................................................................ 43
100BASE-TX Data Path .....................................................................................44
100BASE-TX Reception with No Errors ............................................................. 45
100BASE-TX Reception with Invalid Symbol ..................................................... 45
100BASE-TX Transmission with No Errors ........................................................ 46
100BASE-TX Transmission with Collision .......................................................... 46
Intel® LXT972A Protocol Sublayers ................................................................... 47
LED Pulse Stretching ......................................................................................... 56
Intel® LXT972A Transceiver Typical Twisted-Pair Interface - Switch.................. 60
Intel® LXT972A Transceiver Typical Twisted-Pair Interface - NIC ...................... 61
Intel® LXT972A Transceiver Typical Media Independent Interface.....................62
Intel® LXT972ATransceiver 100BASE-TX Receive Timing.................................68
Intel® LXT972A Transceiver 100BASE-TX Transmit Timing............................... 69
Intel® LXT972A Transceiver 10BASE-T Receive Timing ................................... 70
Intel® LXT972A Transceiver 10BASE-T Transmit Timing .................................. 71
Intel® LXT972A Transceiver 10BASE-T Jabber and Unjabber Timing ..............72
Intel® LXT972A Transceiver 10BASE-T SQE (Heartbeat) Timing .....................73
Intel® LXT972A Transceiver Auto-Negotiation and Fast Link Pulse Timing........ 74
Intel® LXT972A Transceiver Fast Link Pulse Timing .......................................... 74
Intel® LXT972A Transceiver MDIO Input Timing................................................. 75
Intel® LXT972A Transceiver MDIO Output Timing .............................................. 75
Intel® LXT972A Transceiver Power-Up Timing ................................................... 76
Intel® LXT972A Transceiver RESET_L Pulse Width and Recovery Timing........ 77
PHY Identifier Bit Mapping ................................................................................. 81
Intel® LXT972A Transceiver LQFP Package Specifications ............................... 94
Sample LQFP Package - Intel® LXT972A Transceiver ....................................... 95
Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel® LX972A Transceiver.
95
Order Matrix for Intel® LXT972A Transceiver ..................................................... 97
Tables
1
2
3
Related Documents from Intel............................................................................. 11
Intel® LXT972A Transceiver LQFP Numeric Pin List .......................................... 14
Intel® LXT972A Transceiver Signal Types .......................................................... 16
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
5
5 Page 
Intel® LXT972A Single-Port 10/100 Mbps PHY Transceiver
1.0 Introduction to This Document
This document includes information on the Intel® LXT972A Single-Port 10/100 Mbps PHY
Transceiver (called hereafter the LXT972A Transceiver).
1.1
Document Overview
This document includes the following subjects:
• Chapter 2.0, “Block Diagram for Intel® LXT972A Transceiver”
• Chapter 3.0, “Pin Assignments for Intel® LXT972A Transceiver”
• Chapter 4.0, “Signal Descriptions for Intel® LXT972A Transceiver”
• Chapter 5.0, “Functional Description”
• Chapter 6.0, “Application Information”
• Chapter 7.0, “Electrical Specifications”
• Chapter 8.0, “Register Definitions - IEEE Base Registers”
• Chapter 9.0, “Register Definitions - Product-Specific Registers”
• Chapter 10.0, “Intel® LXT972A Transceiver Package Specifications”
• Chapter 11.0, “Product Ordering Information”
1.2 Related Documents
Table 1. Related Documents from Intel
Document Title
Intel® LXT971A , LXT972A , LXT972M Single-Port 10/100 Mbps PHY
Transceivers Specification Update
Intel® LXT971A, LXT972A, and LXT972M 3.3V PHY Transceivers
Design and Layout Guide - Application Note
Magnetic Manufacturers for Networking Product Applications -
Application Note
Document
Number
249354
249016
248991
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
11
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