PDF PLL702-01 Data sheet ( Hoja de datos )

Número de pieza	PLL702-01
Descripción	Clock Generator
Fabricantes	PhaseLink
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No Preview Available ! .com PLL702-01Clock Generator for PowerPC Based Applications et4UFEATURES he• 1 CPU Clock output with selectable frequencies (50, taS66, 75, 80, 83, 90, 100,125 or 133 MHz). a• 1 ASIC output clock (at CPU clock or CPU clock ÷ 2). .D• 2 ASIC output clocks (at CPU clock) w/ output enable. • 1 PCI output clock w/ output enable w• 1 Selectable 48, 30 or 12MHz (USB) output. w• Selectable Spread Spectrum (SST) for EMI reduction w on ASIC and CPU. m• PowerPC compatible output and drive CPU Clock. o• Selectable reduced 67% drive strength on CPU Clock • Advanced, low power, sub-micron CMOS processes. .c• 14.31818MHz fundamental crystal input. • 3.3V and/or 2.5V operation. U• Available in 28-Pin 209mil SSOP (QSOP). t4DESCRIPTIONS eThe PLL702-01 is a low cost, low jitter, and high performance clock synthesizer for generic PowerPC based eapplications. It provides one CPU clock, three ASIC houtputs, one PCI output, and a selectable 48, 30 or 12MHz (USB) output. The user can choose between 9 different SCPU clock frequencies, while the ASIC output can be identical or half of the CPU frequency. Low EMI Spread taSpectrum Technology is available for the CPU, ASIC and PCI clocks. The CPU drive strength is user selectable from a100% to 67%. All frequencies are generated from a single low cost 14.31818MHz crystal. The CPU and ASIC clock .Dcan be driven from an independent 2.5V power supply. BLOCK DIAGRAM PIN ASSIGNMENT (28 pin SSOP) CPUDRV_SEL^ XIN XOUT / ASIC2_OE^ VDD_ANA VDD_DIG VDD_PC I PCI / PCI_SELT GND_PCI GND_USB VDD_USB USB / USB_SELT VDD_ASIC2 ASIC2 A ASIC2 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note : ^: Internal pull-up resistor o: Selectable reduced drive strength 28 CLK_SEL0T 27 CLK_SEL1T 26 SSCO^ 25 SSC1^ 24 GND_ANA 23 GND_CPU 22 CP U o 21 VDD_CPU 20 VDD_ASIC1 19 ASIC1 18 GND_ASIC1 17 ASIC1_SEL^ 16 GND_DIG 15 GND_ASIC2 : Bi-directional pin T: Tri-level input FREQUENCY TABLES CLK_SEL1 0 0 0 M M M 1 1 1 CLK_SEL0 0 M 1 0 M 1 0 M 1 CPU 50 MHz 66 MHz 75 MHz 80 MHz 83 MHz 90 MHz 100 MHz 125 MHz 133 MHz ASIC1 ASIC1_SEL=1 ASIC1_SEL=0 50 MHz 25 MHz 66 MHz 33 MHz 75 MHz 37.5 MHz 80 MHz 40 MHz 83 MHz 41.5 MHz 90 MHz 45 MHz 100 MHz 50 MHz 125 MHz 62.5 MHz 133 MHz 66.5 MHz ASIC2 50 MHz 66 MHz 75 MHz 80 MHz 83 MHz 90 MHz 100 MHz 125 MHz 133 MHz Notes: When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification. PCI output PCI_SEL = 0 PCI_SEL = M PCI_SEL = 1 66 MHz (min. 62.0 MHz) 33 MHz (min. 31.0 MHz) Tri-state (output disabled) wwUSB_SEL w eet4U.comXIN hXOUT taSSSC(0:1) aCLK_SEL(0:1) .DASIC1_SEL PCI_SEL XTAL OSC Control Logic PLL PLL SST DIV 2 ASIC2_OE Control Logic PCI_OE USB VDD_CPU CPU_CLK VDD_ASIC1 ASIC1 VDD_ASIC2 ASIC2(A:B) PCI www47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/09/03 Page 1 1 page PLL702-01 Clock Generator for PowerPC Based Applications VDD Power Up Ramp requirements: At startup, the chip reads a lot of settings for operation according to the application’s requirements. Since reading the settings is done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat controlled to facilitate proper reading of the settings. The important VDD pins are VDD_ANA and VDD_DIG and they should apply to the following two-startup requirements: 1. VDD_DIG should be equally fast or slower than VDD_ANA. VDD_DIG performs a chip reset when VDD has reached a certain level and VDD_ANA should have reached at least up to the same level as well to properly process the reset. 2. The VDD Power Up Ramp of VDD_DIG and VDD_ANA should pass through the section 1.8V to 2.5V no faster than 100µs and with a continuously increasing slope. In this section the tri-level select inputs are read. 3. After VDD Power off, VDD should be allowed to go to 0V and stay there for at least 1ms before a new VDD Power on. It is important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup. VDD off 3.3V GND (0V) 2.2V 2.97V 2.5V 1.8V VDD on No limit Min 1ms Reset enable Min 1s >100us Reset disable 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/09/03 Page 5 5 Page

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