PDF PLL620-07 Data sheet ( Hoja de datos )

Número de pieza	PLL620-07
Descripción	(PLL620-05/06/07/08/09) Low Phase Noise XO
Fabricantes	PhaseLink
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No Preview Available ! .com PLL620-05/-06/-07/-08/-09Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal) t4U Universal Low Phase Noise IC’s heeFEATURES taS• 120MHz to 200MHz Fundamental Mode Crystal. a• Output range: 120 – 200MHz (no multiplication), .D240 – 400MHz (2x multiplier) or 480 – 700MHz w(4x multiplier). w• High yield design support up to 2pF string w capacitance at 200MHz. • CMOS (Standard drive PLL620-07 or Selectable mDrive PLL620-06), PECL (Enable low PLL620-08 oor Enable high PLL620-05) or LVDS output (PLL620-09). .c• Supports 3.3V-Power Supply. • Available in 16-Pin (TSSOP or 3x3mm QFN) UNote: PLL620-06 only available in 3x3mm. Note: PLL620-07 only available in TSSOP. t4DESCRIPTIONS eePLL620-05/-06/-07/-08/-09 are XO IC specifically designed to pull high frequency fundamental hcrystals. Their design was optimized to tolerate higher limits of interelectrodes capacitance and Sbonding capacitance to improve yield. It achieves tavery low current into the crystal resulting in better overall stability. aBLOCK DIAGRAM .DSEL wwOscillator X+ Amplifier w et4U.comX- PLL (Phase Locked Loop) PLL by-pass OE Q Q PIN CONFIGURATION (Top View) VDD XIN XOUT SEL3^ SEL2^ OE GND GND 1 2 3 4 5 6 7 8 16 SEL0^ 15 SEL1^ 14 GND 13 CLKC 12 VDD 11 CLKT 10 GND 9 GND XIN XOUT SEL2^ OE 12 11 10 9 13 8 14 PLL620-0x 7 15 6 16 1 23 5 4 GND CLKC VDD CLKT ^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) OUTPUT ENABLE LOGICAL LEVELS Part # OE State PLL620-08 0 (Default) Output enabled 1 Tri-state PLL620-05 0 Tri-state PLL620-06 PLL620-07 PLL620-09 1 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL620-08 Logical states defined by CMOS levels for PLL620-05/-06/-07/-09 www.DataShe47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/29/02 Page 1 1 page PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal) Universal Low Phase Noise IC’s 8. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL VOD ∆VOD VOH VOL VOS ∆VOS IOXD IOSD CONDITIONS RL = 100 Ω (see figure) Vout = VDD or GND VDD = 0V MIN. 247 -50 0.9 1.125 0 TYP. MAX. 355 454 50 1.4 1.6 1.1 1.2 1.375 3 25 ±1 ±10 -5.7 -8 UNITS mV mV V V V mV uA mA 9. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time SYMBOL tr tf CONDITIONS RL = 100 Ω CL = 10 pF (see figure) MIN. TYP. MAX. UNITS 0.2 0.7 1.0 ns 0.2 0.7 1.0 ns LVDS Levels Test Circuit OUT OUT VOD 50Ω VOS 50Ω LVDS Switching Test Circuit OUT CL = 10pF VDIFF OUT CL = 10pF RL = 100Ω LVDS Transistion Time Waveform OUT OUT 0V (Differential) VDIFF 0V 20% 80% tR 80% 20% tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/29/02 Page 5 5 Page

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PDF Descargar	[ Datasheet PLL620-07.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
PLL620-00	Low Phase Noise XO	PhaseLink
PLL620-05	(PLL620-05/06/07/08/09) Low Phase Noise XO	PhaseLink
PLL620-06	(PLL620-05/06/07/08/09) Low Phase Noise XO	PhaseLink
PLL620-07	(PLL620-05/06/07/08/09) Low Phase Noise XO	PhaseLink

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