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PDF PLL602-10 Data sheet ( Hoja de datos )
| Número de pieza | PLL602-10 | |
| Descripción | Low Phase Noise XO | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL602-10 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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om PLL602-10Preliminary
.c96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
eet4UFEATURES
Sh• Low phase noise output for the 96MHz to
ta400MHz range (-134 dBc at 10kHz offset).
a• Selectable CMOS, PECL and LVDS output.
.D• 12 to 25MHz crystal input.
w• Output Enable selector.
w• 3.3V operation.
w• Available in DIE (65 mil x 62 mil).
mDESCRIPTIONS
.coThe PLL602-10 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
Die, with CMOS, LVDS and PECL output, for 96MHz
Uto 400MHz output range, using a low frequency
t4crystal.
The same die can be used as a XO with output
frequencies ranging from FXIN x 8 to FXIN x 16 thanks
eto selector pads allowing bonding options (see
eDivider Selection Table on this page). This makes
the PLL602-10 ideal for a wide range of applications.
hDIE SPECIFICATIONS
SName
taSize
Reverse side
aPad dimensions
.DThickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
www omBLOCK DIAGRAM
DIE CONFIGURATION
65 mil
(1550,1475)
25 24 23 22 21 20 19 18
17
26 16
15
27
14
28
13
29 12
11
30
10
31 9
1 23 4 5 6 7 8
Y (0,0)
X
MULTIPLIER SELECTION
Pad #19
0
1
MULTIPLIER
FXIN x 16
FXIN x 8
OUTPUT RANGE
192 – 400 MHz
96 – 200 MHz
Note: Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
Pad #25
OUTSEL0
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
OE (Pad #30)
0
1 (Default)
State
Tri-state
Output enabled
eet4U.cSELECT
ShXIN
taXOUT
Reference
Divider
XTAL
OSC
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLKBAR
CLK
www.Da47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 1
1 page  
Preliminary PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
7. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
MIN.
VDD – 1.025
MAX.
VDD – 1.620
UNITS
V
V
8. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN. TYP. MAX. UNITS
0.6 1.5
ns
0.5 1.5
ns
PECL Levels Test Circuit
OUT
50Ω
VDD
2.0V
PECL Output Skew
OUT
50%
OUT
50Ω
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL602-10.PDF ] | |
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