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LM5020SDX-2 데이터시트 PDF




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부품번호 LM5020SDX-2 기능
기능 100V Current Mode PWM Controller
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LM5020SDX-2 데이터시트, 핀배열, 회로
October 2004
LM5020
100V Current Mode PWM Controller
General Description
The LM5020 high voltage pulse-width-modulation (PWM)
controller contains all of the features needed to implement
single ended primary power converter topologies. Output
voltage regulation is based on current-mode control, which
eases the design of loop compensation while providing in-
herent line feed-forward. The LM5020 includes a high-
voltage start-up regulator that operates over a wide input
range up to 100V. The PWM controller is designed for high
speed capability including an oscillator frequency range to
1MHz and total propagation delays less than 100ns. Addi-
tional features include an error amplifier, precision reference,
line under-voltage lockout, cycle-by-cycle current limit, slope
compensation, softstart, oscillator synchronization capability
and thermal shutdown. The controller is available in both
MSOP-10 and LLP-10 packages.
Features
n Internal Start-up Bias Regulator
n Error Amplifier
n Precision Voltage Reference
n Programmable Softstart
n 1A Peak Gate Driver
n Maximum Duty Cycle Limiting (80% for LM5020-1 or
50% for LM5020-2)
n Programmable Line Under Voltage Lockout (UVLO) with
Adjustable Hysteresis
n Cycle-by-Cycle Over-Current Protection
n Slope Compensation (LM5020-1)
n Programmable Oscillator Frequency with
Synchronization Capability
n Current Sense Leading Edge Blanking
n Thermal Shutdown Protection
Packages
n MSOP-10
n LLP-10 (4 mm x 4 mm)
Connection Diagram
Top View
20095001
10-Lead MSOP, LLP
Ordering Information
Order Number
LM5020MM-1
LM5020MMX-1
LM5020SD-1
LM5020SDX-1
LM5020MM-2
LM5020MMX-2
LM5020SD-2
LM5020SDX-2
Description
MSOP, 80% Duty Cycle Limit
MSOP, 80% Duty Cycle Limit
LLP, 80% Duty Cycle Limit
LLP, 80% Duty Cycle Limit
MSOP, 50% Duty Cycle Limit
MSOP, 50% Duty Cycle Limit
LLP, 50% Duty Cycle Limit
LLP, 50% Duty Cycle Limit
NSC Package Drawing
MUB-10A
MUB-10A
SDC-10A
SDC-10A
MUB-10A
MUB-10A
SDC-10A
SDC-10A
Supplied As
1000 Units on Tape and Reel
3500 Units on Tape and Reel
1000 Units on Tape and Reel
4500 Units on Tape and Reel
1000 Units on Tape and Reel
3500 Units on Tape and Reel
1000 Units on Tape and Reel
4500 Units on Tape and Reel
© 2004 National Semiconductor Corporation DS200950
www.national.com




LM5020SDX-2 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to GND
VCC to GND
RT to GND
All other pins to GND
Power Dissipation
ESD Rating (Note 2)
Human Body Model
-0.3V to 100V
-0.3V to 16V
-0.3V to 5.5V
-0.3V to 7V
Internally Limited
2kV
Storage Temperature
Junction Temperature
Operating Ratings
VIN Voltage
External Voltage applied to VCC
Operating Junction Temperature
-55˚C to +150˚C
150˚C
13V to 90V
8V to 15V
-40˚C to +125˚C
Electrical Characteristics
Specifications in standard type face are for TJ= +25˚C and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified: VIN = 48V, VCC = 10V, and RT = 31.6K
Symbol
Parameter
Conditions
Min Typ
Max
Units
Startup Regulator
VCCReg
I-VIN
IIN
VCC Supply
VCC Regulation
VCC Current Limit
Startup Regulator Leakage
Shutdown Current
VCC UVLO (Rising)
Open ckt
(Note 4)
VIN = 100V
VUVLO = 0V, VCC = open
7.4
15
7.7
22
150
250
VccReg VccReg -
- 300mV 100mV
8.0
500
350
V
mA
µA
µA
V
VCC UVLO (Falling)
ICC Supply Current
Error Amplifier
Cload = 0
5.3 6.0
6.7
V
2 3 mA
GBW
Gain Bandwidth
4 MHz
DC Gain
75 dB
Input Voltage
COMP Sink Capability
Line UVLO Shutdown
VFB = COMP
VFB = 1.5V COMP= 1V
1.225
5
1.25
17
1.275
V
mA
Shutdown Threshold
1.225
1.25
1.275
V
Undervoltage Shutdown
16 20 24 µA
Hysteresis Current Source
Current Limit
ILIM Delay to Output
CS step from 0 to 0.6V
30
ns
Time to onset of OUT
Transition (90%)
CS Cycle by Cycle CS Threshold
0.45
0.5
0.55
V
Voltage
Leading Edge Blanking Time
50 ns
CS Sink Impedance (clocked)
35 55
Soft Start
Softstart Current Source
7 10 13 µA
Softstart to COMP Offset
0.35
0.55
0.75
V
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LM5020SDX-2 전자부품, 판매, 대치품
Detailed Operating Description
The LM5020 High Voltage PWM controller contains all of the
features needed to implement single ended primary power
converter topologies. The LM5020 includes a high-voltage
startup regulator that operates over a wide input range to
100V. The PWM controller is designed for high speed capa-
bility including an oscillator frequency range to 1MHz and
total propagation delays less than 100ns. Additional features
include an error amplifier, precision reference, line under-
voltage lockout, cycle-by-cycle current limit, slope compen-
sation, softstart, oscillator sync capability and thermal shut-
down. The functional block diagram of the LM5020 is shown
in Figure 1. The LM5020 is designed for current-mode con-
trol power converters, which require a single drive output,
such as Flyback and Forward topologies. The LM5020 pro-
vides all of the advantages of current-mode control including
line feed-forward, cycle-by-cycle current limiting and simpli-
fied loop compensation .
High Voltage Start-Up Regulator
The LM5020 contains an internal high voltage startup regu-
lator, that allows the input pin (Vin) to be connected directly
to line voltages as high as 100V. The regulator output is
internally current limited to 15mA. When power is applied,
the regulator is enabled and sources current into an external
capacitor connected to the VCC pin. The recommended ca-
pacitance range for the Vcc regulator is 0.1µF to 100µF.
When the voltage on the VCC pin reaches the regulation
level of 7.7V, the controller output is enabled. The controller
will remain enabled until VCC falls below 6V.
In typical applications, a transformer auxiliary winding is
connected through a diode to the VCC pin. This winding
should raise the VCC voltage above 8V to shut off the internal
startup regulator. Powering VCC from an auxiliary winding
improves conversion efficiency while reducing the power
dissipated in the controller. The external VCC capacitor must
be selected such that the capacitor maintains the Vcc volt-
age greater than the VCC UVLO falling threshold (6V) during
the initial start-up. During a fault condition when the con-
verter auxiliary winding is inactive, external current draw on
the VCC line should be limited such that the power dissipated
in the start-up regulator does not exceed the maximum
power dissipation capability of the controller.
An external start-up or other bias rail can be used instead of
the internal start-up regulator by connecting the VCC and the
Vin pins together and feeding the external bias voltage (8-
15V) to the two pins.
Line Under Voltage Detector
The LM5020 contains a line Under Voltage Lock Out (UVLO)
circuit. An external set-point voltage divider from Vin to GND
sets the operational range of the converter. The resistor
divider must be designed such that the voltage at the UVLO
pin is greater than 1.25V when Vin is in the desired operating
range. If the under voltage threshold is not met, all functions
of the controller are disabled and the controller remains in a
low power standby state.
UVLO hysteresis is accomplished with an internal 20µA
current source that is switched on or off into the impedance
of the set-point divider. When the UVLO threshold is ex-
ceeded, the current source is activated to instantly raise the
voltage at the UVLO pin. When the UVLO pin voltage falls
below the 1.25V threshold the current source is turned off,
causing the voltage at the UVLO pin to fall. The UVLO pin
can also be used to implement a remote enable / disable
function. If an external transistor pulls the UVLO pin below
the 1.25V threshold, the converter will be disabled.
Error Amplifier
An internal high gain error amplifier is provided within the
LM5020. The amplifier’s non-inverting input is internally set
to a fixed reference voltage of 1.25V. The inverting input is
connected to the FB pin. In non-isolated applications, the
power converter output is connected to the FB pin via volt-
age scaling resistors. Loop compensation components are
connected between the COMP and FB pins. For most iso-
lated applications the error amplifier function is implemented
on the secondary side of the converter and the internal error
amplifier is not used. The internal error amplifier is config-
ured as an open drain output and can be disabled by con-
necting the FB pin to ground. An internal 5K pull-up resistor
between a 5V reference and COMP can be used as the
pull-up for an optocoupler in isolated applications.
Current Limit/Current Sense
The LM5020 provides a cycle-by-cycle over current protec-
tion function. Current limit is accomplished by an internal
current sense comparator. If the voltage at current sense
comparator input exceeds 0.5V, the output will be immedi-
ately terminated. A small RC filter, located near the control-
ler, is recommended to filter noise from the current sense
signal. The CS input has an internal MOSFET which dis-
charges the CS pin capacitance at the conclusion of every
cycle. The discharge device remains on an additional 50ns
after the beginning of the new cycle to attenuate the leading
edge spike on the current sense signal.
The LM5020 current sense and PWM comparators are very
fast, and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and
sense resistor. The capacitor associated with the CS filter
must be located very close to the device and connected
directly to the pins of the controller (CS and GND). If a
current sense transformer is used, both leads of the trans-
former secondary should be routed to the sense resistor and
the current sense filter network. A sense resistor located in
the source of the primary power MOSFET may be used for
current sensing, but a low inductance resistor is required.
When designing with a current sense resistor all of the noise
sensitive low power ground connections should be con-
nected together local to the controller and a single connec-
tion should be made to the high current power ground (sense
resistor ground point).
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