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PDF NT256S72V89A0G Data sheet ( Hoja de datos )
| Número de pieza | NT256S72V89A0G | |
| Descripción | 256MB SDRAM Module | |
| Fabricantes | Nanya Technology | |
| Logotipo |  |
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NT256S72V89A0G
256MB : 32M x 72
mUnbuffered SDRAM Module
.co32Mx72 bit One Bank Unbuffered SDRAM Module
based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
et4UFeatures
hel 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
Sl Intended for PC133 applications
ta- Clock Frequency: 133MHz
a- Clock Cycle: 7.5ns
.D- Clock Assess Time: 5.4ns
l Inputs and outputs are LVTTL (3.3V) compatible
wl Single 3.3V ± 0.3V Power Supply
wl Single Pulsed RAS interface
wl SDRAMs have 4 internal banks
l
l
l
l
Automatic and controlled Precharge commands
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
Suspend Mode and Power Down Mode
8192 Refresh cycles distributed across 64ms
l Module has 1 physical bank
l Fully Synchronous to positive Clock Edge
ml Data Mask for Byte Read/Write control
l Auto Refresh (CBR) and Self Refresh
l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect with Write Protect
.coDescription
NT256S72V89A0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMM) which is organized as 32Mx72
Uhigh-speed memory arrays and is configured as one 32M x 72 physical bank. The DIMM uses nine 32Mx8 SDRAMs in 400mil TSOP II
packages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
t4supports the JEDEC 1N rule while allowing very low burst power.
eAll control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK2). Internal operating modes are defined by combinations
eof RAS , CAS , WE , S0 / S2 , DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 15-bit
haddress bus accepts address information in a row / column multiplexing arrangement.
SPrior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
tathe two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.
.DaOrdering Information
Part Number
Organization
wwwNT256S72V89A0G-7K
MHz.
143MHz
133MHz
133MHz
Speed
CL
3
2
3
t RCD
3
2
3
t RP
3
2
3
Leads
Power
NT256S72V89A0G-75B
NT256S72V89A0G-8B
* CL = CAS Latency
32Mx72
Preliminary 09 / 2001
100MHz
125MHz
100MHz
222
om3 3 3
.c2 2 2
Gold
3.3V
w.DataSheet4U1
w © NANYA TECHNOLOGY CORP.
wNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
NT256S72V89A0G
256MB : 32M x 72
Unbuffered SDRAM Module
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Notes
VDD Power Supply Voltage
-0.3 to +4.6
VIN Input Voltage
-0.3 to VDD +0.3
V1
VOUT
Output Voltage
-0.3 to VDD +0.3
TA Operating Temperature (ambient)
0 to +70
°C 1
TSTG
Storage Temperature
-55 to +125
°C 1
PD Power Dissipation
9 W1
IOUT
Short Circuit Output Current
50 mA 1
1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (T A =0 to 70 °C)
Symbol
Parameter
VDD Power Voltage
VIH Input High Voltage
VIL Input Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
I IL Input Leakage current
1. All voltages referenced to VSS .
2. VIH (max) = VDD / VDDQ + 1.2V for pulse width ≤ 5ns
3. VIL (min) = VSS / VSSQ - 1.2V for pulse width ≤ 5ns .
Min.
3.0
2.0
-0.3
2.4
-
-10
Rating
Typ.
3.3
-
-
-
-
-
Capacitance (T A =25 °C , f =1MHz, V DD =3.3 ± 0.3V)
Symbol
Parameter
CI1
CI2
CI3
CI4
CI5
CI6
CIO1
CIO2
Input Capacitance (A0-A9, A10/AP, A11, BA0, BA1, RAS , CAS , WE )
Input Capacitance (CKE0)
Input Capacitance ( S0 - S2 )
Input Capacitance (CK0 - CK3)
Input Capacitance (DQMB0 - DQMB7)
Input Capacitance (SA0 - SA2, SCL, WP)
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
Input/Output Capacitance (SDA)
Max.
3.6
VDD + 0.3
0.8
-
0.4
10
Units
V
V
V
V
V
uA
Notes
1
1,2
1,3
Max.
77
58
33
40
21
9
10
11
Unit
pF
DC Output Load Circuit
Output
50 pF
3.3 V
1200 ohms
870 ohms
VOH(DC) = 2.4V,IOH= -2mA
VOL(DC) = 0.4V,IOL= -2mA
Preliminary 09 / 2001
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
NT256S72V89A0G
256MB : 32M x 72
Unbuffered SDRAM Module
Serial Presence Detect -- Part 2 of 2
32Mx72 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V SDRAMs with SPD
Byte Description
64-71 Manufacturer’s JEDED ID Code
72 Module Manufacturing Location
73-90 Module Part number
91-92 Module Revision Code
93-94 Module Manufacturing Data
95-98 Module Serial Number
99-125 Reserved
126 Modules Supports this Clock Frequency
127 Attributes for Clock Frequency defined in byte 126
128-255 Open for customer Use
1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
3. NANYA 11decimal (bank four) 0000 1011 binary 0B Hex.
SPD Entry Value
-7K -75B -8B
NANYA
N/A
N/A N/A N/A
N/A
Year/Week Code
Serial Number
Undefined
100MHz
CK0, CK2,CL3, CL2
Concurrent AP
Undefined
Serial PD Data Entry
(Hexadecimal)
-7K -75B -8B
7F7F7F0B00000000
00
00 00 00
00
yy/ww
00
00
64
AF
00
Note
3
1,2
Preliminary 09 / 2001
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
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