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PDF NT256D72S89AKGU Data sheet ( Hoja de datos )
| Número de pieza | NT256D72S89AKGU | |
| Descripción | 256MB DDR SDRAM DIMM | |
| Fabricantes | Nanya Technology | |
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NT256D72S89AKGU
256MB : 32M x 72
omLow Profile Registered DDR SDRAM DIMM
U.c184pin Low Profile Registered DDR SDRAM MODULE Based on 32Mx8 DDR SDRAM
eet4Features
h• 32Mx72 Low Profile Registered DDR DIMM based on 32Mx8
SDDR SDRAM
ta• JEDEC Standard 184-pin Dual In-Line Memory Module
a• Error Check Correction (ECC) Support
.D• Phase-lock loop (PLL) clock driver to reduce loading
w• Registered inputs with one-clock delay
w• Performance:
w PC1600 PC2100
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- Device CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
Speed Sort
DIMM CAS Latency*
-8B -75B -7K Unit
3 3.5 3
f CK Clock Frequency
100 133 133 MHz
mt CK Clock Cycle
10 7.5 7.5 ns
of DQ DQ Burst Frequency 200 266 266 MHz
• Intended for 100 MHz and 133 MHz applications
.c• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• SDRAMs have 4 internal banks for concurrent operation
U• Differential clock inputs
*
t4One clock cycle added for registered DIMMs to account for input register.
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
Description
eNT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module
e(DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II
hpackages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these
Scommon design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance,
taflexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to
a266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the
.DDIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
wserial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
wOrdering Information
wPart Number
Speed
Organization Leads
Power
NT256D72S89AKGU-7K
NT256D72S89AKGU-75B
NT256D72S89AKGU-8B
REV 1.1
12/2002
143MHz (7ns @ CL = 2.5)
133MHz (7.5ns @ CL= 2)
133MHz (7.5ns @ CL= 2.5)
100MHz (10ns @ CL = 2)
125MHz (8ns @ CL = 2.5)
100MHz (10ns @ CL = 2)
mDDR266A
PC2100
U.coDDR266B
PC2100
et4DDR200
PC1600
32Mx72
Gold
2.5V
.DataShe1
w © NANYA TECHNOLOGY CORP.
wwNANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
1 page  
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
Serial Presence Detect -- Part 1 of 2
32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry (Hexadecimal) Note
Byte
Description
DDR266A DDR266B DDR200 DDR266A DDR266B DDR200
-7K -75B -8B
-7K -75B -8B
Number of Serial PD Bytes Written during
0
Production
128
80
1 Total Number of Bytes in Serial PD device
256
08
2 Fundamental Memory Type
SDRAM DDR
07
3 Number of Row Addresses on Assembly
13
0D
4 Number of Column Addresses on Assembly
11
0A
5 Number of DIMM Bank
1 01
6. Data Width of Assembly
X72 48
7 Data Width of Assembly (cont’)
X72
00
8 Voltage Interface Level of this Assembly
SSTL 2.5V
04
9 DDR SDRAM Device Cycle Time at CL=2.5
7ns
7.5ns
8ns
70
75
80
DDR SDRAM Device Access Time from
10
0.75ns 0.75ns
0.8ns
75
75
80
Clock at CL=2.5
11 DIMM Configuration Type
ECC
02
12 Refresh Rate/Type
7.8us / SR
82
13 Primary DDR SDRAM Width X8 08
14 Error Checking DDR SDRAM Device Width
X8
08
DDR SDRAM Device Attr: Min CLk Delay,
15
Random Col Access
1 Clock
01
DDR SDRAM Device Attributes:
16
Burst Length Supported
2, 4, 8
0E
DDR SDRAM Device Attributes: Number of
17
Device Banks
4
04
DDR SDRAM Device Attributes: CAS
18
Latencies Supported
2/2.5
2/2.5
2/2.5
0C
0C
0C
19 DDR SDRAM Device Attributes: CS Latency
0
01
20 DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR SDRAM Device Attributes:
Differential Clock, PLL, REGISTER
26
22 DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23 Minimum Clock Cycle at CL=2
7.5ns
10ns
10ns
75
A0
A0
Maximum Data Access Time from Clock at
24
0.75ns 0.75ns
0.8ns
75
75
80
CL=2
25 Minimum Clock Cycle Time at CL=1
N/A
00
Maximum Data Access Time from Clock at
26
CL=1
N/A
00
27 Minimum Row Precharge Time (tRP)
20ns
20ns
30ns
50
50
78
Minimum Row Active to Row Active delay
28
15ns
15ns
15ns
3C
3C
3C
(tRRD)
29 Minimum RAS to CAS delay (tRCD)
20ns
20ns
30ns
50
50
78
30 Minimum RAS Pulse Width (tRAS)
45ns
45ns
50ns
2D
2D
32
31 Module Bank Density
512MB
40
Address and Command Setup Time Before
32
0.9ns
0.9ns
1.1ns
90
90
B0
Clock
Address and Command Hold Time After
33
0.9ns
0.9ns
1.1ns
90
90
B0
Clock
34 Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
50
50
60
35 Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
50
50
60
36-61 Reserved
Undefined
00
62 SPD Revision
Initial
Initial
Initial
00
00
00
63 Checksum Data
A7 D7 AD
REV 1.1
12/2002
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
tAC
tDQSCK
tCH
tCL
tCK
tCK
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time
CL=2.5
CL=2
-7K
Min. Max.
-0.75 +0.75
-0.75 +0.75
0.45 0.55
0.45 0.55
7 12
7.5 12
-75B
Min. Max.
-0.75 +0.75
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5 12
10 12
-8B
Min. Max.
-0.8 +0.8
-0.8 +0.8
0.45 0.55
0.45 0.55
8 12
10 12
tDH DQ and DM input hold time
0.5
0.5
0.6
tDS DQ and DM input setup time
tDIPW
tHZ
DQ and DM input pulse width (each
input)
Data-out high-impedance time from
CK/CK
tLZ
tDQSQ
tDQSQA
tHP
Data-out low-impedance time from
CK/CK
DQS-DQ skew (DQS & associated
DQ signals)
DQS-DQ skew (DQS & all DQ
signals)
Minimum half clk period for any given
cycle; defined by clk high (tCH )
or clk low (tCL ) time
tQH Data output hold time from DQS
tDQSS
tDQSL,H
tDSS
tDSH
tMRD
Write command to 1st DQS latching
transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Mode register set command cycle
time
tWPRES Write preamble setup time
tWPST
tWPRE
tIH
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
0.5
1.75
-0.75
-0.75
tCH
or
tCL
tHP -
0.75ns
0.75
0.35
0.2
0.2
14
0
0.40
0.25
0.9
+0.75
+0.75
0.5
0.5
1.25
0.60
0.5
1.75
-0.75
-0.75
tCH
or
tCL
tHP -
0.75ns
0.75
0.35
0.2
0.2
15
0
0.40
0.25
1.1
+0.75
+0.75
0.5
0.5
1.25
0.60
Address and control input setup time
tIS 0.9
(fast slew rate)
1.1
Address and control input hold time
tIH 1.0
(slow slew rate)
1.1
0.6
2
-0.8
-0.8
tCH
or
tCL
tHP -
1.0ns
0.75
0.35
0.2
0.2
16
0
0.40
0.25
1.1
1.1
1.1
+0.8
+0.8
0.6
0.6
1.25
0.60
Unit Notes
ns 1-4
ns 1-4
tCK 1-4
tCK 1-4
ns 1-4
ns 1-4
1-4,
ns
15, 16
1-4,
ns
15, 16
ns 1-4
ns 1-4, 5
ns 1-4, 5
ns 1-4
ns 1-4
tCK 1-4
tCK 1-4
tCK 1-4
tCK 1-4
tCK 1-4
tCK 1-4
ns 1-4
ns 1-4, 7
tCK 1-4, 6
tCK 1-4
2-4,
ns 9, 11,
12
2-4,
ns 9, 11,
12
2-4,
ns 10-12,
14
REV 1.1
12/2002
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NT256D72S89AKGU.PDF ] | |
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