PDF AS7C34096LL Data sheet ( Hoja de datos )

Número de pieza	AS7C34096LL
Descripción	Low Power CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! .com$GYDQFHLQIRUPDWLRQ $6&// t4U ® ee 9.ð,QWHOOLZDWWORZSRZHU&02665$0 Sh)HDWXUHV ta• Organization: 524,288 words × 8 bits • Intelliwatt™ active power circuitry a• 2.7V to 3.6V operating range .D• 25/35/55/70/100 ns address access time w• Low power consumption - Active: 126 mW max (100 ns cycle) at 3.6V w - Standby: 288 µW max w - Very low DC component in active power, 200 µA m• 1.5V data retention • Easy memory expansion with CE, OE inputs • Smallest footprint packages - 48 ball FBGA - 400 mil 44-pin TSOP II • Center power and ground pins for low noise • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • Industrial temperature range available (-40 to +85°C) • Other voltage versions available - 2.3V to 3.0V (AS7C254096LL) - 1.65V to 1.95V (AS7C184096LL) .co/RJLFEORFNGLDJUDP UVDD t4VSS Input buffer eA0 A1 eA2 A3 1024 × 512 × 8 A4 Array hA5 A6 (4,194,304) A7 SA8 A9 ww.DataColumn decoder I/O7 Control Circuit I/O0 WE OE CE 3LQDUUDQJHPHQWWRSYLHZ TSOP II NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VDD I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC 48-CSP Ball-Grid-Array Package (shading indicates no ball) 123456 A A0 A1 NC A3 A6 A8 B I/O4 A2 WE A4 A7 I/O0 C I/O5 NC A5 I/O1 D VSS VDD E VDD VSS F I/O6 A18 A17 I/O2 G I/O7 OE CE A16 A15 I/O3 H A9 A10 A11 A12 A13 A14 w .com6HOHFWLRQJXLGH U-25 -35 -55 -70 -100 Unit t4Maximum address access time 25 35 55 70 100 ns eeMaximum output enable access time 10 10 10 10 10 ns hMaximum operating current 110 80 50 45 35 mA taSMaximum CMOS standby current 80 80 80 80 80 µA www.Da',' $ $//,$1&(6(0,&21'8&725 Copyright ©1998 Alliance Semiconductor. All rights reserved. 1 page $GYDQFHLQIRUPDWLRQ $6&// ® :ULWHF\FOH Parameter Symbol Write cycle time Chip enable to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in High Z Output active from write end tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW 25 Min Max 25 – 15 – 15 – 0– 15 – 0– 10 – 0– –5 1– 35 Min Max 35 – 15 – 15 – 0– 15 – 0– 10 – 0– –5 1– 55 Min Max 55 – 15 – 15 – 0– 15 – 0– 10 – 0– –5 1– 70 Min Max 70 – 15 – 15 – 0– 15 – 0– 10 – 0– –5 1– 100 Min Max Unit Notes 100 – ns 15 – ns 12 15 – ns 0 – ns 12 15 – ns 0 – ns 10 – ns 0 – ns 4, 5 – 5 ns 4, 5 1 – ns 4, 5 :ULWHZDYHIRUP10,11 Address WE Din Dout tAS tWC tAW tWP tWZ tAH tDW Data valid tOW tDH :(FRQWUROOHG :ULWHZDYHIRUP10,11 Address CE tAS tWC tAW tCW tAH &(FRQWUROOHG tWP WE tWZ tDW tDH Din Data valid Dout ',' $ $//,$1&(6(0,&21'8&725 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AS7C34096LL	Low Power CMOS SRAM	Alliance Semiconductor

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