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T-51513D104JU-FW_A_AC 데이터시트 PDF




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T-51513D104JU-FW_A_AC 데이터시트, 핀배열, 회로
.comLCD Module Technical Specification
heet4UType No. T-51513D104JU-FW-A-AC
First Edition
Jun 18, 2003
Final Revision
******
www.DataS Approved by (Quality Assurance Division)
Checked by (ACI Engineering Division)
omPrepared by (Module Administration Group)
U.cNo. Item
t4-- CONTENTS
1 OVERVIEW
ee2 ABSOLUTE MAXIMUM RATINGS
h3 ELECTRICAL CHARACTERISTICS
4 INTERFACE PIN CONNECTION
taS5 INTERFACE TIMING
6 BLOCK DIAGRAM
a7 MECHANICAL SPECIFICATION
.D8 OPTICAL CHARACTERISTICS
9 RELIABILITY TEST CONDITION
w10 INSPECTION STANDARDS
w11 HANDLING PRECAUTIONS FOR TFT-LCD MODULE
w-- PACKAGING SPECIFICATION
Page
1
2
3
4
6
6
10
11
14
16
17
18
21
m-- PRODUCT NUMBER LABELING FORM
.co-- LAMP UNIT FOR 10.4” VGA
24
26
www.DataSheet4UT-51513D104JU-FW-A-AC (AC) No. 2003-0100
OPTREX CORPORATION
Page 1/31




T-51513D104JU-FW_A_AC pdf, 반도체, 판매, 대치품
*1) Lamp Current measurement method (The current meter is inserted in low voltage line.)
CTL
A
LCD
Module
CTH
CTL
CTH
A
Inverter
Power
Supply
*2) Lamp frequency of inverter may produce interference with horizontal synchronous frequency, and
this may cause horizontal beat on the display. Therefore, please adjust lamp frequency, and keep
inverter as far from module as possible or use electronic shielding between inverter and module to
avoid the interference.
*3) Lamp life time is defined as the time either when the brightness becomes 50% of the initial value, or
when the starting lamp voltage does not meet the value specified in this table.
*4) The life time of the backlight depends on the ambient temperature. The life time will decrease under
low/high temperature.
*5) Please use the inverter which has symmetrical current wave form as follows,
The degree of unbalance: less than 10%
The ratio of wave height: less than 2 ±10%
IPH IPH: High side peak The degree of unbalance = |IPH - IPL| / Irms × 100(%)
IPL IPL: Low side peak The ratio of wave height = IPH(or I PL) / Irms
CURRENT WAVE FORM
[Note]
A) Power and signals sequence:
t1 10 ms
0 < t2 50 ms
0 < t3 50 ms
400 ms t4
200 ms t5
0 t6
0. 9V CC
VCC
data
0.1VCC
0. 9VCC
0.1VCC 0.1VCC
t1 t2
Backlight
t3
t4
t5 t6
data: RGB DATA, DCLK, HD, VD, DENA
T-51513D104JU-FW-A-AC (AC) No. 2003-0100
OPTREX CORPORATION
Page 4/31

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T-51513D104JU-FW_A_AC 전자부품, 판매, 대치품
5. INTERFACE TIMING
(1) Timing Specifications
ITEM
SYMBOL MIN.
TYP.
MAX.
UNIT
Frequency
fCLK
--
25
29 MHz
DCLK
*1) *4)
Period
Low Width
High Width
tCLK
34.5
40
--
ns
tWCL
12
--
-- ns
tWCH
12
--
-- ns
DATA *1) Set up time
(R,G,B,DENA
HD, VD) Hold time
tDS 5 -- -- ns
tDH 5 -- -- ns
Horizontal Active Time tHA
640
640
640
tCLK
Horizontal Front Porch tHFP
10
16
-- tCLK
DENA Horizontal Back Porch
tHBP
2
138
--
tCLK
*3) Vertical Active Time tVA 480 480 480
tH
Vertical Front Porch
tVFP
1
13
--
tH
Vertical Back Porch
tVBP
2
33
--
tH
HD
*2)*4)
Frequency
Period
Low Width
fH
tH
tWHL
27
26.3
5
31.5
31.7
96
38
37.0
--
kHz
µs
tCLK
Frequency
fV 55 60 70 Hz
VD *2) Period
tV 14.3 16.7 18.2
ms
[Note]
Low Width
tWVL
3
--
--
tH
*1) DATA is latched at fall edge of DCLK in this specification.
*2) Polarities of HD and VD are negative in this specification.
*3) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
*4) DCLK should appear during all invalid period, and HD should appear during invalid period of
frame cycle.
T-51513D104JU-FW-A-AC (AC) No. 2003-0100
OPTREX CORPORATION
Page 7/31

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