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AT45DB161D 데이터시트 PDF




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부품번호 AT45DB161D 기능
기능 16-Megabit 2.7-volt Only Serial DataFlash
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AT45DB161D 데이터시트, 핀배열, 회로
Features
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
RapidSSerial Interface: 66 MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 512 Bytes per Page
– 528 Bytes per Page
Page Program Operation
– Intelligent Programming Operation
– 4,096 Pages (512/528 Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (512 Bytes)
– Block Erase (4 Kbytes)
– Sector Erase (128 Kbytes)
Two SRAM Data Buffers (512/528 Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7 mA Active Read Current Typical
– 25 µA Standby Current Typical
– 9 µA Deep Power Down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
16-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB161D
1. Description
The AT45DB161D is a 2.5-volt or 2.7-volt, serial-interface sequential access Flash
memory ideally suited for a wide variety of digital voice-, image-, program code- and
data-storage applications. The AT45DB161D supports RapidS serial interface for
applications requiring very high speed operations. RapidS serial interface is SPI com-
patible for frequencies up to 66 MHz. Its 17,301,504 bits of memory are organized as
4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the
AT45DB161D also contains two SRAM buffers of 512/528 bytes each. The buffers
allow the receiving of data while a page in the main Memory is being reprogrammed,
as well as writing a continuous data stream. EEPROM emulation (bit or byte alterabil-
ity) is easily handled with a self-contained three step read-modify-write operation.
Unlike conventional Flash memories that are accessed randomly with multiple
address lines and a parallel interface, the DataFlash uses a RapidS serial interface to
3500D–DFLASH–02/06




AT45DB161D pdf, 반도체, 판매, 대치품
3. Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (512/528 BYTES)
BUFFER 1 (512/528 BYTES)
BUFFER 2 (512/528 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB161D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
4,096/4,224 bytes
SECTOR 0
SECTOR 0b = 248 Pages
126,976/130,944 bytes
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR 1 = 256 Pages
131,072/135,168 bytes
SECTOR 2 = 256 Pages
131,072/135,168 bytes
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
SECTOR 14 = 256 Pages
131,072/135,168 bytes
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
8 Pages
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 15 = 256 Pages
131,072/135,168 bytes
BLOCK 510
BLOCK 511
Block = 4,096/4,224 bytes
PAGE 4,094
PAGE 4,095
Page = 512/528 bytes
4 AT45DB161D
3500D–DFLASH–02/06

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AT45DB161D 전자부품, 판매, 대치품
AT45DB161D
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.
6.4 Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 4,096 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the standard DataFlash page size (528 bytes), an opcode
of D2H must be clocked into the device followed by three address bytes (which comprise the 24-
bit page and byte address sequence) and 4 don’t care bytes. The first 12 bits (PA11 - PA0) of
the 22-bit address sequence specify the page in main memory to be read, and the last 10 bits
(BA9 - BA0) of the 22-bit address sequence specify the starting byte address within that page.
To start a page read from the binary page size (512 bytes), the opcode D2H must be clocked
into the device followed by three address bytes and 4 don’t care bytes. The first 12 bits (A20 -
A9) of the 21-bits sequence specify which page of the main memory array to read, and the last 9
bits (A8 - A0) of the 21-bits address sequence specify the starting byte address within the page.
The don’t care bytes that follow the address bytes are sent to initialize the read operation. Fol-
lowing the don’t care bytes, additional pulses on SCK result in data being output on the SO
(serial output) pin. The CS pin must remain low during the loading of the opcode, the address
bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is
reached, the device will continue reading back at the beginning of the same page. A low-to-high
transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
maximum SCK frequency allowable for the Main Memory Page Read is defined by the fSCK
specification. The Main Memory Page Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
6.5 Buffer Read
The SRAM data buffers can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four
opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read
Command. The use of each opcode depends on the maximum SCK frequency that will be used
to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to
the maximum specified by fCAR1. The D1H and D3H opcode can be used for lower frequency
read operations up to the maximum specified by fCAR2.
To perform a buffer read from the standard DataFlash buffer (528 bytes), the opcode must be
clocked into the device followed by three address bytes comprised of 14 don’t care bits and 10
buffer address bits (BFA9 - BFA0). To perform a buffer read from the binary buffer (512 bytes),
the opcode must be clocked into the device followed by three address bytes comprised of 15
don’t care bits and 9 buffer address bits (BFA8 - BFA0). Following the address bytes, one don’t
care byte must be clocked in to initialize the read operation. The CS pin must remain low during
the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data.
When the end of a buffer is reached, the device will continue reading back at the beginning of
the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pin (SO).
3500D–DFLASH–02/06
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