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PDF KS32C50100 Data sheet ( Hoja de datos )
| Número de pieza | KS32C50100 | |
| Descripción | Interrupt Controller | |
| Fabricantes | Samsung | |
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KS32C50100 RISC MICROCONTROLLER
13 INTERRUPT CONTROLLER
INTERRUPT CONTROLLER
The KS32C50100 interrupt controller has a total of 21 interrupt sources. Interrupt requests can be generated by
internal function blocks and at external pins.
The ARM7TDMI core recongnizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast interrupt
request (FIQ). Therefore all KS32C50100 interrupts can be categorized as either IRQ or FIQ. The KS32C50100
interrupt controller has an interrupt pending bit for each interrupt source.
omFour special registers are used to control interrupt generation and handling:
.c• Interrupt priority registers. The index number of each interrupt source is written to the pre-defined interrupt
priority register field to obtain that priority. The interrupt priorities are pre-defined from 0 to 20.
• Interrupt mode register. Defines the interrupt mode, IRQ or FIQ, for each interrupt source.
U• Interrupt pending register. Indicates that an interrupt request is pending. If the pending bit is set, the interrupt
t4pending status is maintained until the CPU clears it by writing a "1" to the appropriate pending register. When
the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". The
eservice routine must clear the pending condition by writing a "1" to the appropriate pending bit. This avoids the
possibility of continuous interrupt requests from the same interrupt pending bit.
e• Interrupt mask register. Indicates that the current interrupt has been disabled if the corresponding mask bit is
h"1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the global mask bit (bit 21) is set to
"1", no interrupts are serviced. However, the source's pending bit is set if the interrupt is generated. When the
www.DataSglobal mask bit has been set to "0", the interrupt is serviced.
www.DataSheet4U.c1o3-m1
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KS32C50100 RISC MICROCONTROLLER
INTERRUPT CONTROLLER
INTERRUPT MASK REGISTER
The interrupt mask register, INTMSK, contains interrupt mask bits for each interrupt source.
Register
INTMSK
Offset Address
0x4008
Table 13-4 INTMSK Register
R/W Description
R/W Interrupt mask register
Reset Value
0x003FFFFF
31
INTMSK
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GXX XX XX XX XX XXX XX XX XX XX
[20:0] Individual interrupt mask bits
NOTE: Each of the 21 bits in the interrupt mask register, INTMSK,
(except for the global mask bit, G) corresponds to an interrupt
source. When a source interrupt mask bit is 1, the interrupt is not
serviced by the CPU when the corresponding interrupt request is
generated. If the mask bit is 0, the interrupt is serviced upon
request. And if global mask bit (bit 21) is 1, no interrupts are
serviced. (However, the source pending bit is set whenever the
interrupt is generated.) After the global mask bit is cleared, the
interrupt is serviced. The 21 interrupt sources are mapped as
follows:
[20] I 2C interrupt
[19] Ethernet controller MAC Rx interrupt
[18] Ethernet controller MAC T x interrupt
[17] Ethernet controller BDMA Rx interrupt
[16] Ethernet controller BDMA Tx interrupt
[15] HDLC channel B Rx interrupt
[14] HDLC channel B Tx interrupt
[13] HDLC channel A Rx interrupt
[12] HDLC channel A Tx interrupt
[11] Timer 1 interrupt
[10] Timer 0 interrupt
[9] GDMA channel 1 interrupt
[8] GDMA channel 0 interrupt
[7] UART1 receive & error interrupt
[6] UART1 transmit interrupt
[5] UART0 receive & error interrupt
[4] UART0 transmit interrupt
[3] External interrupt 3
[2] External interrupt 2
[1] External interrupt 1
[0] External interrupt 0
[21] Global interrupt mask bit
0 = Enable interrupt requests
1 = Disable all interrupt requests
Figure 13-3 Interrupt Mask Register (INTMSK)
13-5
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