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SIS630 데이터시트 PDF




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SIS630 데이터시트, 핀배열, 회로
SiS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Content
1 SiS630 Overview .....................................................................................................1
1.1 Function Block Reference Table................................................................3
2 Features..................................................................................................................5
3 Pin Assignment......................................................................................................12
3.1 Pin Assignment (Top View).....................................................................12
3.1.1 SiS630 Pin Assignment (Top View-Left Side) ...................................12
3.1.2 SiS630 Pin Assignment (Top View-Right Side).................................13
m3.2 SiS630 Alphabetical Pin List ...................................................................14
3.3 Power Plane..........................................................................................20
o3.4 Muxpin..................................................................................................21
.c4 Pin Description (Preliminary) ..................................................................................23
4.1 Host Bus Interface .................................................................................23
4.2 DRAM Controller....................................................................................27
U4.3 PCI Interface .........................................................................................27
4.4 PCI IDE Interface...................................................................................32
t44.5 VGA Interface........................................................................................33
4.6 Power management Interface.................................................................36
e4.7 SMBus Interface ....................................................................................37
4.8 Keyboard controller Interface..................................................................38
e4.9 LPC Interface ........................................................................................39
4.10 RTC Interface ........................................................................................39
h4.11 AC’ 97 interface......................................................................................40
S4.12 Fast Ethernet and Homenetworking interface ..........................................41
4.13 USB interface ........................................................................................43
ta4.14 Legacy I/o and Miscellaneous Signals.....................................................44
4.15 Power and Ground Signals .....................................................................44
5 Hardware Trap.......................................................................................................46
a6 Function Description ..............................................................................................49
6.1 MA Mapping Table .................................................................................49
.D6.1.1 SDRAM/System Memory................................................................49
6.1.2 SDRAM/FBC .................................................................................50
6.1.3 VCM/System Memory ....................................................................51
w6.1.4 VCM/FBC......................................................................................54
6.2 PSON# and ACPILED Description ..........................................................55
w6.2.1 ACPI.............................................................................................57
w6.3 Power States for SiS630 Signals.............................................................58
6.4 Arbiter Tree ...........................................................................................62
6.5 Nand Tree Test Scheme.........................................................................63
om7 Register Summary / Description – Core Logic..........................................................67
.c7.1 Device 0, Function 0 ( Host-to-PCI Bridge) ..............................................67
7.1.1 Configuration Space Header...........................................................67
t4U7.1.2 Registers for Host & DRAM ............................................................68
7.1.3 Shadow RAM & PCI-Hole Area.......................................................69
www.DataSheePreliminary V.10 Oct.07,1999
i Silicon Integrated Systems Corporation




SIS630 pdf, 반도체, 판매, 대치품
SiS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Figure
Figure 1-1 SiS630 System Block Diagram .........................................................................2
Figure 1-2 SiS630: Ready for Easy PC .............................................................................3
Figure 6.2-1 PSON#.......................................................................................................56
Figure 6.2-2 ACPILED ...................................................................................................57
Figure 6.4-1 Arbiter Tree ................................................................................................62
Figure 6.5-1 The Mechanism of NAND Tree...................................................................63
Figure 6.5-2 The Test Scheme of NAND Tree ................................................................64
Figure 13.4-1 Receive Filter Algorithm........................................................................... 267
Figure 16.2-1 GPIOx Logic ........................................................................................... 348
Figure 20.2-1 SiS630 A Temp vs Power(2) .................................................................... 392
Table
TABLE 6.5-1 Nand Tree List for SiS630
Table 9.1-1 Sync Polarity vs. Vertical Screen Resolution................................................. 142
Table 9.1-2 Table for Video Clock Selection ................................................................... 142
Table 9.3-1 Table of Sequencer Registers...................................................................... 153
Table 9.4-2 Table of Function Select.............................................................................. 157
Table 9.4-3 Table of Rotate Count................................................................................. 157
Table 9.4-4 Table for Write Mode................................................................................... 158
Table 9.4-5 Table of Memory Address Select ................................................................. 158
Table 9.5-1 Table of Attribute Controller Registers.......................................................... 160
Table 9.5-2 Table for Video Read-back Through Diagnostic Bit (I) ................................... 162
Table 9.5-3 Table for Video Read-back Through Diagnostic Bit (II) .................................. 162
Table 9.5-4 Table of Pixel Panning ................................................................................ 162
Table 9.7-1 Table of Extended Registers........................................................................ 165
Table 9.8-2 Table of digital video interface registers........................................................ 171
Table11.1-1 Interrupt Pin Reroute Table......................................................................... 186
Table 18.1-1 Absolute Maximum Ratings....................................................................... 387
Table 18.2-1 DC Characteristics of Host, DRAM, PCI and IDE Interface ......................... 387
Table 18.2-1 Table of DC Characteristics for DAC .......................................................... 388
Preliminary V.10 Oct.07,1999
iv Silicon Integrated Systems Corporation

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SIS630 전자부품, 판매, 대치품
SiS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
1 SiS630 Overview
The single chipset, SiS630, provides a high performance/low cost Desktop solution for the
Intel Slot 1 and socket 370 series CPUs based system by integrating a high performance
North Bridge, advanced hardware 2D/3D GUI engine and Super-South bridge. In addition,
SiS630 provides system-on-chip solution that complies with Easy PC Initiative which supports
Instantly Available/OnNow PC technology, USB, Legacy Removal and Slotless Design and
FlexATX form factor.
By integrating the UltraAGPTM technology and advanced 128-bit graphic display interface,
SiS630 delivers AGP 4x performance and up to 2 GB/s memory bandwidth. Furthermore,
SiS630 provides powerful hardware decoding DVD accelerator to improve the DVD playback
performance. In addition to providing the standard interface for CRT monitors, SiS630 also
provides the Digital Flat Panel Port (DFP) for a standard interface between a personal
computer and a digital flat panel monitor. To extend functionality and flexibility, SiS also
provides the “ Video Bridge” (SiS301) to support the NTSC/PAL Video Output, Digital LCD
Monitor and Secondary CRT Monitor, which reduces the external Panel Link transmitter and
TV-Out encoder for cost effected solution. SiS630 also adopts Share System Memory
Architecture which can flexibly utilize the frame buffer size up to 64MB.
The “ Super-South Bridge” in SiS630 integrates all peripheral controllers/accelerators
/interfaces. SiS630 provides a total communication solution including 10/100Mb Fast Ethernet
for Office requirement and 1Mb HomePNA for Home Networking. SiS630 offers AC’ 97
compliant interface that comprises digital audio engine with 3D-hardware accelerator, on-chip
sample rate converter, and professional wavetable along with separate modem DMA
controller. SiS630 also provides interface to Low Pin Count (LPC) operating at 33 MHz clock
which is the same as PCI clock on the host, and dual USB host controller with five USB ports
that deliver better connectivity and 2 x 12Mb bandwidth.
The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the Ultra DMA33/66
function that supports the data transfer rate up to 66 MB/s. It provides the separate data path
for two IDE channels that can eminently improve the performance under the multi-tasking
environment.
The following illustrates the system block diagram.
Preliminary V.10 Oct.07,1999
1 Silicon Integrated Systems Corporation

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