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부품번호 | GE28F256K18 기능 |
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기능 | (GE28FxxxKx) Intel StrataFlash Memory (J3) | ||
제조업체 | Intel Corporation | ||
로고 | |||
전체 30 페이지수
Intel StrataFlash® Synchronous Memory
(K3/K18)
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3,
28F256K18 (x16)
Datasheet
Product Features
■ Performance
m—110/115/120 ns Initial Access Speed for
64/128/256 Mbit Densities
o—25 ns Asynchronous Page-Mode Reads,
8 Words Wide
.c—13 ns Synchronous Burst-Mode Reads,
8 or 16 Words Wide
— 32-Word Write Buffer
U—Buffered Enhanced Factory
Programming
t4■ Software
— 25 µs (typ.) Program and Erase Suspend
eLatency Time
— Flash Data Integrator (FDI), Common
eFlash Interface (CFI) Compatible
— Programmable WAIT Signal Polarity
h■ Quality and Reliability
— Operating Temperature:
S–40 °C to +85 °C
— 100K Minimum Erase Cycles per Block
ata—0.18 µm ETOX™ VII Process
■ Architecture
— Multi-Level Cell Technology: High
Density at Low Cost
— Symmetrical 64 K-Word Blocks
— 256 Mbit (256 Blocks)
— 128 Mbit (128 Blocks)
— 64 Mbit (64 Blocks)
— Ideal for “CODE + DATA” applications
■ Security
— 2-Kbit Protection Register
— Unique 64-bit Device Identifier
— Absolute Data Protection with VPEN and
WP#
— Individual and Instantaneous Block
Locking, Unlocking and Lock-Down
Capability
■ Packaging and Voltage
— 64-Ball Intel® Easy BGA Package
(128-Mbit is also offered in a lead-free
package)
— 56-and 79-Ball Intel® VF BGA Package
— VCC = 2.70 V to 3.60 V
— VCCQ = 1.65 to 1.95 V/2.375 to 3.60 V
The Intel StrataFlash® Synchronous Memory (K3/K18) product line adds a high performance
.Dburst-mode interface and other additional features to the Intel StrataFlash® memory family of
products. Just like its J3 counterpart, the K3/K18 device utilizes reliable and proven two-bit-per-
cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost.
wThis is Intel’s third generation MLC technology, manufactured on 0.18 µm lithography, making
it the most widely used and proven MLC product family on the market.
wK3/K18 is a 3-volt device (core), but it is available with 3-volt (K3) or 1.8-volt (K18) I/O
mvoltages. These devices are ideal for mainstream applications requiring large storage space for
w oboth code and data storage. Advanced system designs will benefit from the high performance
.cpage and burst modes for direct execution from the flash memory. Available in densities from 64
Mbit to 256 Mbit (32 Mbyte), the K3/K18 device is the highest density NOR-based flash
t4Ucomponent available today, just as it was when Intel introduced the original device in 1997.
heeNotice: This document contains information on new products in production. The specifications
Sare subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
.DataOrder Number: 290737-009
www February 2005
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.0
11.0
12.0
13.0
14.0
4
9.1.3 Output Disable ....................................................................................... 36
9.1.4 Standby .................................................................................................. 36
9.1.5 Reset ...................................................................................................... 36
9.2 Device Commands .............................................................................................. 37
Read Modes................................................................................................................ 39
10.1 Asynchronous Page-Mode Read ........................................................................ 39
10.2 Synchronous Burst-Mode Read .......................................................................... 40
10.3 Read Configuration Register ............................................................................... 40
10.3.1 Read Mode............................................................................................. 41
10.3.2 Latency Count ........................................................................................ 41
10.3.3 WAIT Polarity ......................................................................................... 43
10.3.4 Data Hold ............................................................................................... 43
10.3.5 WAIT Delay ............................................................................................ 44
10.3.6 Burst Sequence...................................................................................... 44
10.3.7 Clock Edge ............................................................................................. 44
10.3.8 Burst Length ........................................................................................... 44
Program Modes......................................................................................................... 45
11.1
11.2
11.3
11.4
11.5
Word Programming ............................................................................................. 45
Write-Buffer Programming .................................................................................. 45
Program Suspend ............................................................................................... 46
Program Resume ................................................................................................ 47
Buffered Enhanced Factory Programming (Buffered-EFP)................................. 47
11.5.1 Buffered-EFP Requirements and Considerations .................................. 47
11.5.2 Buffered-EFP Setup Phase .................................................................... 48
11.5.3 Buffered-EFP Program and Verify Phase .............................................. 48
11.5.4 Buffered-EFP Exit Phase ....................................................................... 49
Erase Mode ................................................................................................................. 50
12.1 Block Erase ......................................................................................................... 50
12.2 Erase Suspend.................................................................................................... 50
12.3 Erase Resume .................................................................................................... 51
Security Modes ......................................................................................................... 52
13.1 Block Locking Operations ................................................................................... 52
13.1.1 Block Lock .............................................................................................. 53
13.1.2 Block Unlock .......................................................................................... 53
13.1.3 Block Lock-Down ................................................................................... 53
13.1.4 Block Lock During Erase Suspend......................................................... 53
13.1.5 WP# Lock-Down Control ........................................................................ 53
13.2 Protection Registers ............................................................................................ 54
13.2.1 Reading the Protection Registers .......................................................... 55
13.2.2 Programming the Protection Registers .................................................. 55
13.2.3 Locking the Protection Registers ........................................................... 55
13.3 Array Protection .................................................................................................. 55
Special Modes ........................................................................................................... 56
14.1 Read Status Register .......................................................................................... 56
14.1.1 Clear Status Register ............................................................................. 57
14.2 Read Device Identifier ......................................................................................... 57
Datasheet
4페이지 1.0
1.1
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Introduction
This document contains information pertaining to the Intel StrataFlash® Synchronous Memory
(K3/K18) device. The purpose of this document is to describe the features, operations and
specifications of these devices.
Nomenclature
3 Volt core:
3 Volt I/O:
1.8 Volt I/O:
AMIN:
AMAX:
Block:
Program:
VPEN:
VPEN:
CUI:
OTP:
PR:
PLR:
RFU:
SR:
RCR:
WSM:
MLC:
Set:
Clear:
VCC range of 2.7 V – 3.6 V
VCCQ range of 2.375 V – 3.6 V
VCCQ range of 1.65 V – 1.95 V
For Easy BGA packages: AMIN = A1
For VF BGA packages: AMIN = A0
For Easy BGA packages:
64 Mbit AMAX = A22
128 Mbit AMAX = A23
256 Mbit AMAX = A24
For VF BGA packages:
64 Mbit AMAX = A21
128 Mbit AMAX = A22
256 Mbit AMAX = A23
A group of flash cells that share common erase circuitry and erase simultaneously
To write data to the flash array
Refers to a signal or package connection name
Refers to timing or voltage levels
Command User Interface
One Time Programmable
Protection Register
Protection Lock Register
Reserved for Future Use
Status Register
Read Configuration Register
Write State Machine
Multi-Level Cell
Indicates a logic one (1)
Indicates a logic zero (0)
Datasheet
7
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부품번호 | 상세설명 및 기능 | 제조사 |
GE28F256K18 | (GE28FxxxKx) Intel StrataFlash Memory (J3) | Intel Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |