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PDF MT88L89 Data sheet ( Hoja de datos )
| Número de pieza | MT88L89 | |
| Descripción | 3V Integrated DTMFTransceiver with Adaptive Micro Interface | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
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® MT88L89
3V Integrated DTMF Transceiver
Advance Information with Adaptive Micro Interface
Features
ISSUE 1
May 1995
• Central office quality DTMF transmitter/
receiver
Ordering Information
MT88L89AE
20 Pin Plastic DIP
• Low voltage operation (2.7-3.6V)
MT88L89AC
20 Pin Ceramic DIP
• Adjustable guard time
MT88L89AS
20 Pin SOIC
• Automatic tone burst mode
• Call progress tone detection to -30dBm
m• Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs
o• DTMF transmitter/receiver power down via
.cregister control
Applications
U• Credit card systems
t4• Paging systems
• Repeater systems/mobile radio
e• Interconnect dialers
e• Personal computers
hDescription
SThe MT88L89 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
tatechnology offering low power consumption and high
reliability.
MT88L89AN
24 Pin SSOP
MT88L89AP
28 Pin PLCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features. The transmitter and receiver may
independently be powered down via register control.
.DaTONE
∑
D/A
Converters
www omIN+
.cIN-
t4UGS
eOSC1
taSheOSC2
Tone Burst
Gating Cct.
+ Dial
- Tone
Filter
Oscillator
Circuit
Bias
Circuit
Control
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Row and
Column
Counters
Digital
Algorithm
and Code
Converter
Steering
Logic
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
www.DaVDD VRef VSS
ESt St/GT
Figure 1 - Functional Block Diagram
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
4-125
1 page  
Advance Information
MT88L89
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
VDD
St/GT
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
C1
R1
ESt
VDD
St/GT
R2
a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
tGTA = (RpC1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
C1
R1
ESt
R2
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (tGTP) and
tone absent (tGTA) guard times. This may be
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.
Increasing tREC improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short tREC with a long tDO would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
Call Progress Filter
A call progress mode, using the MT88L89, can be
selected allowing the detection of various tones,
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
EVENTS
Vin
ESt
St/GT
RX0-RX3
b3
tREC
A
B
tREC
TONE #n
tDP
tGTP
CD
tID
TONE
#n + 1
tDA
E
tDO
TONE
#n + 1
tGTA
DECODED TONE # (n-1)
tPStRX
#n
tPStb3
# (n + 1)
F
VTSt
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
4-129
5 Page 
Advance Information
MT88L89
BIT NAME
DESCRIPTION
b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1 RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power down mode.
b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7. Control Register B Description
BIT NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0 IRQ
b1 TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Pause duration has terminated
and transmitter is ready for new
data.
Interrupt is inactive. Cleared after
Status Register is read.
Cleared after Status Register is
read or when in non-burst mode.
b2 RECEIVE DATA REGISTER Valid data is in the Receive Data Cleared after Status Register is
FULL
Register.
read.
b3 DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8. Status Register Description
4-135
11 Page | ||
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