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STA015 데이터시트 PDF




ST Microelectronics에서 제조한 전자 부품 STA015은 전자 산업 및 응용 분야에서
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부품번호 STA015 기능
기능 (STA015x) MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
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STA015 데이터시트, 핀배열, 회로
STA015
STA015B STA015T
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
– All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
m– Lower sampling frequencies syntax exten-
osion, (not specified by ISO) called MPEG 2.5
.cDECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2
USAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:
t448, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III
eELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
eKbit/s
hADPCM CODEC CAPABILITIES:
– sample frequency from 8 kHz to 32 kHz
S– sample size from 8 bits to 32 bits
– encoding algorithm: DVI,
taITU-G726 pack (G723-24, G721,G723-40)
– Tone control and fast-forward capability
aEASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
.D(TQFP44 & LFBGA 64)
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
wBYPASS MODE FOR EXTERNAL AUDIO
SOURCE
wSERIAL BITSTREAM INPUT INTERFACE
wEASY PROGRAMMABLE ADC INPUT
SO28
TQFP44
LFBGA64
ORDERING NUMBER: STA015$ (SO28)
STA015T$ (TQFP44)
STA015B$ (LFBGA 8x8)
INDICATORS
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decod-
ing Layer III compressed elementary streams, as
specified in MPEG 1 and MPEG 2 ISO standards.
The device decodes also elementary streams
compressed by using low sampling rates, as spec-
INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C
INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S AND
OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
March 2004
ified by MPEG 2.5. STA015 receives the input
mdata through a Serial input Interface. The decoded
osignal is a stereo, mono, or dual channel digital
.coutput that can be sent directly to a D/A converter,
Uby the PCM Output Interface.
t4This interface is software programmable to adapt
ethe STA015 digital output to the most common
eDACs architectures used on the market. The func-
htional STA015 chip partitioning is described in
SFig.1a and Fig.1b.
www.Data 1/55




STA015 pdf, 반도체, 판매, 대치품
STA015 STA015B STA015T
1.0 OVERVIEW
1.1 MP3 decoder engine
The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and
MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCIL-
LARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order
to implement specific functions.
Decoded audio data goes through a software volume control and a two-band equalizer blocks before feed-
ing the output I2S interface. This results in no need for an external audio processor.
MP3 bitstream is sent to the decoder using a simple serial input interface (see pins SDI, SCKR, BIT_EN
and DATA_REQ), supporting input rate up to 20 Mbit/s. Received data are stored in a 256 bytes long input
buffer which provides a feedback line (see DATA_REQ pin) to the bitstream source (tipically an MCU).
1.2 ADPCM encoder/decoder engine
This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates
(from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits).
During encoding process two different interfaces can be used to feed data: the serial input interface (same
interface used also to feed MP3 bitstream) or the ADC input interface, which provides a seamless con-
nection with an external A/D converter. The currently used interface is selected via I2C bus.
Also to retrieve encoded data two different interfaces are available: the I2C bus or the faster GPSO output
interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins
(GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target applica-
tion.
1.3 BYPASS functional mode
In order to allow using the device to post-process auxiliary audio sources a special BYPASS mode is avail-
able. When the device is configured in BYPASS mode the embedded DSP will process digital audio data
coming through the ADC input interface and will output the resulting data to the external DAC.
Available processings include volume and a tone ontrols.
THERMAL DATA
Symbol
Parameter
Rth j-amb Thermal resistance Junction to Ambient
Value
85
Unit
°C/W
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Power Supply
Vi Voltage on Input pins
VO
Tstg
Toper
Voltage on output pins
Storage Temperature
Operative ambient temp
Value
-0.3 to 4
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-40 to +150
-20 to +85
Unit
V
V
V
°C
°C
4/55

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STA015 전자부품, 판매, 대치품
STA015 STA015B STA015T
Figure 3. Test Circuit
OUT_CLK/DATA_REQ
VDD
100nF
VSS
VDD
100nF
VSS
VDD
100nF
VSS
VDD
100nF
VDD PVDD VSS
4.7µF
4.7µF
VSS PVSS
28
1
2
14
13
16
15
23
22
17 18
100nF
PVDD
PVSS
26
RESET
3
4
9
10
11
12
5
6
7
25
8
27
21
20
19
24
TESTEN
SDA
SCL
SDO
SCKT
LRCKT
OCLK
SDI
SCKR
BIT_EN
SDI_ADC
SCR_INT
LRCK_ADC
XTI
XTO
470pF
10K
1K
4.7nF
D00AU1143
PVSS
Figure 4. Test Load Circuit
VDD
IOL
OUTPUT
CL
IOH
VREF
Test Load
Output
SDA
Other Outputs
IOL IOH CL
1mA
100pF
100µA 100µA 100pF
VREF
3.6V
1.5V
D98AU967
2.0 FUNCTIONAL DESCRIPTION
2.1 Clock Signal
The STA015 input clock is derivated from an external source or from a industry standard crystal oscillator,
generating input frequencies of 10, 14.31818 or 14.7456 MHz.
Other frequencies may be supported upon request to STMicroelectronics. Each frequency is supported
by downloading a specific configuration file, provided by STM XTI is an input Pad with specific levels.
Symbol
VIL
VIH
Parameter
Low Level Input Voltage
High Level Input Voltage
Test Condition
Min.
VDD-0.8
Typ.
Max.
VDD-1.8
Unit
V
V
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